參數(shù)資料
型號(hào): DS1856E-025R
廠商: Maxim Integrated Products, Inc.
英文描述: Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors and Password Protection
中文描述: 雙路,溫度與內(nèi)部校準(zhǔn)監(jiān)視器和控制電阻器,密碼保護(hù)
文件頁數(shù): 4/31頁
文件大?。?/td> 484K
代理商: DS1856E-025R
D
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
4
_____________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
0
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
20 + 0.1C
B
0.6
4.0
TYP
MAX
400
100
UNITS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 13)
SCL Clock Frequency (Note 9)
f
SCL
kHz
Bus Free Time Between STOP and
START Condition (Note 9)
t
BUF
μs
Hold Time (Repeated)
START Condition (Notes 9, 10)
t
HD:STA
μs
LOW Period of SCL Clock (Note 9)
t
LOW
μs
H G H P er od of S C L C ock ( N ote 9)
t
HIGH
μs
0.9
Data Hold Time (Notes 9, 11, 12)
t
HD:DAT
μs
Data Setup Time (Note 9)
t
SU:DAT
ns
START Setup Time (Note 9)
t
SU:STA
μs
300
1000
300
300
Rise Time of Both SDA and SCL
Signals (Note 13)
t
R
ns
Fall Time of Both SDA and SCL
Signals (Note 13)
t
F
ns
Setup Time for STOP Condition
t
SU:STO
μs
Capacitive Load for Each Bus Line
EEPROM Write Time
C
B
t
W
400
20
pF
ms
10
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.85V to 5.5V, T
A
= -40°C to +95°C, unless otherwise noted. See Figure 6.)
Note 1:
Note 2:
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 3:
SDA and SCL are connected to V
CC
and all other input signals are connected to well-defined logic levels.
Note 4:
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the volt-
age on the inputs is greater than full scale.
Note 5:
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum V
CC
voltage.
Note 6:
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7:
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8:
See the
Typical Operating Characteristics
.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns = 1250ns
before the SCL line is released.
All voltages are referenced to ground.
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