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參數(shù)資料
| 型號： | DS1854E-050 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES TEMP-CNTRL 50/50K 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 50 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
DS1854
Dual Temperature-Controlled
Resistors with Two Monitors
4
_____________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode (Note 9)
0
400
SCL Clock Frequency
fSCL
Standard mode (Note 9)
0
100
kHz
Fast mode (Note 9)
1.3
Bus Free Time Between STOP and
START Condition
tBUF
Standard mode (Note 9)
4.7
s
Fast mode (Notes 9, 10)
0.6
Hold Time (Repeated)
START Condition
tHD:STA
Standard mode (Notes 9, 10)
4.0
s
Fast mode (Note 9)
1.3
Low Period of SCL Clock
tLOW
Standard mode (Note 9)
4.7
s
Fast mode (Note 9)
0.6
High Period of SCL Clock
tHIGH
Standard mode (Note 9)
4.0
s
Fast mode (Notes 9, 11, 12)
0
0.9
Data Hold Time
tHD:DAT
Standard mode (Notes 9, 11, 12)
0
s
Fast mode (Note 9)
100
Data Setup Time
tSU:DAT
Standard mode (Note 9)
250
ns
Fast mode (Note 9)
0.6
Start Setup Time
tSU:STA
Standard mode (Note 9)
4.7
s
Fast mode (Note 13)
20 + 0.1CB
300
Rise Time of Both SDA and SCL
Signals
tR
Standard mode (Note 13)
20 + 0.1CB
1000
ns
Fast mode (Note 13)
20 + 0.1CB
300
Fall Time of Both SDA and SCL
Signals
tF
Standard mode (Note 13)
20 + 0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP Condition
tSU:STO
Standard mode
4.0
s
Capacitive Load for Each Bus Line
CB
(Note 13)
400
pF
EEPROM Write Time
tW
(Note 14)
10
ms
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.)
Note 1:
All voltages are referenced to ground.
Note 2:
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
Note 3:
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
Note 4:
The maximum voltage the MON inputs will read is approximately 2.5V, even if the voltage on the inputs are
greater than 2.5V.
Note 5:
This voltage is defining the maximum range of the analog-to-digital converter and not the maximum
VCC voltage.
Note 6:
Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a
straight line from measured minimum position to measured maximum position.
Note 7:
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change
is the slope of the straight line from measured minimum position to measured maximum position.
Note 8:
See the Typical Operating Characteristics.
Note 9:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns
before the SCL line is released.
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