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參數(shù)資料
| 型號(hào)： | DS1851E-010TR |
| 英文描述： | Dual Temperature-Controlled NV Digital-to-Analog Converters |
| 中文描述： | 雙溫控非易失數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大?。?/td> | 202K |
| 代理商： | DS1851E-010TR |
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DS1851
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Sequential Address Read
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1851 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1851.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a STOP condition. The master does
not respond with a zero.
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1851 operates as
a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA and SCL. Timing diagrams for the 2-wire
serial port can be found in Figures 3 and 4. Timing information for the 2-wire serial port is provided in
the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy:
Both data and clock lines remain high.
Start data transfer:
A change in the state of the data line from high to low while the clock is high
defines a START condition.
Stop data transfer:
A change in the state of the data line from low to high while the clock line is high
defines the STOP condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1852 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Optical Transceiver Diagnostic Monitor |
| DS1852B-000 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DS1852B-000/C | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DS1852B-000/T&R | 制造商:Maxim Integrated Products 功能描述:IC MONITOR TXRX OPTICAL 25-BGA |
| DS1852B-000/T&R | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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