參數(shù)資料
型號(hào): DS1851E-010
英文描述: Dual Temperature-Controlled NV Digital-to-Analog Converters
中文描述: 雙溫控非易失數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 17/17頁(yè)
文件大?。?/td> 202K
代理商: DS1851E-010
DS1851
17 of 17
NOTES:
1.
All voltages are referenced to ground.
2.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
3.
After this period, the first clock pulse is generated.
4.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
5.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VI
H MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
6.
C
B
- total capacitance of one bus line in pF, timing referenced to (0.9)(V
CC
) and (0.1)(V
CC
).
7.
EEPROM-write begins after a STOP condition occurs.
8.
Measured with SDA = SCL = V
rc
= V
CC
, and V
rg
= GND. The outputs OutV and OutG are left open.
9.
Valid at 25
°
C only.
10.
With V
rc
= V
CC
-1.25 and V
rg
= 1.25 + GND.
11.
0.8% is equivalent to 2 LSB.
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