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參數(shù)資料
| 型號： | DS1847E-050+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES TEMP-CNTRL 50/10K 16TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k，50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 850 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1847
16 of 17
NOTES:
1. All voltages are referenced to ground.
2. Inputs SDA = SCL = WP = VCC. A0, A1, and A2, must be tied to VCC or GND.
3. Valid at 25°C only.
4. Absolute linearity is the difference of measured value from expected value at DAC position.
Expected value is a straight line from measured minimum position to measured maximum position.
5. Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change.
Expected LSB change is the slope of the straight line from measured minimum position to measured
maximum position.
6. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released.
7. After this period, the first clock pulse is generated.
8. The maximum t
HD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
V
IHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
10. C
B – total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.
11. EEPROM write begins after a STOP condition occurs.
12. The temperature coefficient varies with resistor position from 650ppm/°C at position FFh to
1000ppm/°C at 00h (for the 50k resistor), or 1500ppm/°C at 00h (for the 10k resistor). See the graphs
below. The tempco can be significantly reduced by using the resistor calibration values. When doing
so, the average tempco over the entire temperature range is between 200ppm°/C (for the lower
positions) and 10ppm/°C (higher positions). Refer to the Programming the Look-Up Table section of
the data sheet.
13. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
14. Refer to Programming the Look-Up Table section of the data sheet for calibration.
15. Address input A1 passes Latch-up per JEDEC 78 class I. All other pins pass class II.
ORDERING INFORMATION
TEMPCO vs. RESISTANCE
10K RESISTOR
500
600
700
800
900
1000
1100
1200
1300
1400
1500
0
2000
4000
6000
8000
10000
RESISTANCE (OHMS)
PPM/
°C
TEMPCO vs. RESISTANCE
50K RESISTOR
500
600
700
800
900
1000
1100
0
10000
20000
30000
40000
50000
RESISTANCE (OHMS)
PPM/
°C
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