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參數(shù)資料
| 型號(hào)： | DS1845E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT/MEM DUAL NV 10K 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1845
2 of 14
PIN DESCRIPTIONS
Name TSSOP BGA
Description
VCC
14
A3
Power Supply Terminal. The DS1845 will support supply
voltages ranging from +2.7V to +5.5V.
GND
7
D1
Ground Terminal.
SDA
1
B2
2-Wire serial data interface. The serial data pin is for serial data
transfer to and from the DS1845. The pin is open drain and may
be wire-ORed with other open drain or open collector interfaces.
SCL
2
A2
2-Wire Serial Clock Input. The serial clock input is used to
clock data into the DS1845 on rising edges and clock data out on
falling edges.
WP
6
C1
Write Protect Input. If set to logic 0, the data in memory and the
potentiometer wiper setting may be changed. If set to logic 1, both
the memory and the potentiometer wiper settings will be write
protected. The WP pin is pulled high internally.
A0
3
A1
Address Input. Pins A0, A1, and A2 are used to specify the
address of each DS1845 when used in a multi-dropped
configuration. Up to eight DS1845s may be addressed on a single
2-wire bus.
A1
4
B1
Address Input.
A2
5
C2
Address Input.
H0
13
A4
High terminal of Potentiometer 0. For both potentiometers, it is
not required that the high terminal be connected to a potential
greater than the low terminal. Voltage applied to the high terminal
of each potentiometer cannot exceed VCC or go below ground.
H1
11
B3
High terminal of Potentiometer 1.
L0
8
D3
Low terminal of Potentiometer 0. For both potentiometers, it is
not required that the low terminal be connected to a potential less
than the high terminal. Voltage applied to the low terminal of each
potentiometer cannot exceed VCC or go below ground.
L1
10
C4
Low terminal of Potentiometer 1.
W0
9
D4
Wiper terminal of Pot 0. The wiper position of Potentiometer 0
is determined by the byte at EEPROM memory location F9h.
Voltage applied to the wiper terminal of each potentiometer cannot
exceed the power supply voltage, VCC, or go below ground.
W1
12
B4
Wiper terminal of Pot 1. The wiper position of Potentiometer 1
is determined by the byte at EEPROM memory location F8h.
NC
C3
No Connect.
NC
D2
No Connect.
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