參數(shù)資料
型號(hào): DS1806
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字電位計(jì)
英文描述: Digital Sextet Potentiometer(數(shù)字六位電位器)
文件頁數(shù): 4/8頁
文件大?。?/td> 59K
代理商: DS1806
DS1806
022698 4/8
3–WIRE SERIAL PORT TIMING
Figure 4
RST
CLK
D
IN
C
OUT
LSB
t
CC
t
CH
t
RLT
t
HLT
t
CDH
t
DC
CASCADE OPERATION
A feature of the DS1806 is the ability to control multiple
devices from a single processor. Multiple DS1806s can
be linked or daisy chained as shown in Figure 5. As a
data bit is entered into the I/O shift register of the
DS1806, a bit will appear at the C
OUT
terminal before a
maximum delay of 50 nanoseconds. The LSB of poten-
tiometer–1 will always be the first out of the part at the
beginning of a transaction. Additionally, the C
OUT
termi-
nal is always active regardless of the state RST. Howev-
er, D
IN
and CLK inputs are ignored when RST is in the
low state.
The C
OUT
output of the DS1806 can be used to drive the
D
IN
input of another DS1806. When cascading multiple
devices, the total number of bits transmitted is always
48 multiplied by the total number of DS1806s being cas-
caded.
An optional feedback resistor can be placed between
the C
OUT
terminal of the last device and the first DS1806
D
IN
input, which allows the controlling processor to
read, as well as, write data, or circularly clock data
through the daisy chain. The value of the feedback or
isolation resistor should be in the range from 1K
to
10K
.
To read data, the reading device configures itself as an
input and monitors the state of the D
IN
line, which is driv-
en by C
OUT
through the isolation resistor. When RST is
driven high, bit 48 is present on the C
OUT
pin, which is
fed back to the input D
IN
pin through the isolation resis-
tor. When the CLK input transitions low to high, bit 48 is
loaded into the first position of the I/O shift register and
bit 47 becomes present on C
OUT
and D
IN
of the next de-
vice. After 48 bits (or 48 times the number of the
DS1806s in the daisy chain), the data has shifted com-
pletely around and back to its original position. When
RST transitions to the low state to end data transfer, the
value (the same as before the read occurred) is loaded
in the shift register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between
the actual measured output voltage and the expected
output voltage. Absolute linearity is given in terms of a
minimum increment or expected output when the wiper
is moved one position. The DS1806 is specified to have
an absolute linearity of
±
0.50 LSB.
Relative linearity is a measure of error between two ad-
jacent wiper position points. The DS1806 is specified to
have a relative linearity of
±
0.25 LSB.
TYPICAL APPLICATION CONFIGURATIONS
Figure 6 shows the typical application configuration of
the DS1806 as a fixed gain attenuator. In this configura-
tion, the DS1806 adjusts the attenuation level of the in-
coming signal. Variations in wiper resistance are mini-
mized by connecting the wiper terminal of the part to a
high impedance load. Depending on voltage across the
wiper, its resistance may vary from 400 ohms to
1000 ohms. Note that the resistance R1 in Figure 6
should be chosen to be much greater than the wiper re-
sistance R
W
.
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