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參數(shù)資料
| 型號： | DS1803 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Addressable Dual Digital Potentiometer(可尋址雙路數(shù)字電位器) |
| 中文描述： | DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 74K |
| 代理商： | DS1803 |
DS1803
022698 3/10
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP
conditions is not limited, and is determined by the mas-
ter device. The information is transferred byte–wise and
each receiver acknowledges with a ninth bit.
Within the bus specifications a regular mode (100 KHz
clock rate) and a fast mode (400 KHz clock rate) are
defined. The DS1803 works in both modes.
Acknowledge:
addressed, is obliged to generate an acknowledge after
the reception of each byte. The master device must
generate an extra clock pulse which is associated with
this acknowledge bit.
Each
receiving
device,
when
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
1.
Data transfer from a master transmitter to a
slave receiver:
The first byte transmitted by the
master is the control byte (slave address). Next fol-
lows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2.
Data transfer from a slave transmitter to a mas-
ter receiver:
The first byte (the slave address) is
transmitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will
not be released.
The DS1803 may operate in the following two modes:
1.
Slave receiver mode:
Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START
and STOP conditions are recognized as the begin-
ning and end of a serial transfer. Address recogni-
tion is performed by hardware after reception of the
slave address and direction bit.
2.
Slave transmitter mode:
The first byte is received
and handled as in the slave receiver mode. How-
ever, in this mode the direction bit will indicate that
the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1803 while the serial
clock is input on SCL. START and STOP conditions
are recognized as the beginning and end of a serial
transfer.
SLAVE ADDRESS
A control byte is the first byte received following the
START condition from the master device. The control
byte consist of a four bit control code; for the DS1803,
this is set as 0101 binary for read/write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device to
select which of eight devices are to be accessed. The
select bits are in effect the three least significant bits of
the slave address. Additionally, A2, A1 and A0 can be
changed anytime during a powered condition of the
part. The last bit of the control byte (R/W*) defines the
operation to be performed. When set to a one a read
operation is selected, and when set to a zero a write
operation is selected. Figure 3 shows the control byte
structure for the DS1803.
Following the START condition, the DS1803 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving the 0101 address code and
appropriate device select bits, the slave device outputs
an acknowledge signal on the SDA line.
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參數(shù)描述 |
|---|---|
| DS18030-010 | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS18030-010+ | 功能描述:數(shù)字電位計 IC Addressable Dual RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS18030-050 | 功能描述:數(shù)字電位計 IC RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS18030-050+ | 功能描述:數(shù)字電位計 IC Addressable Dual RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1803-010 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Addressable Dual Digital Potentiometer |
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