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參數(shù)資料
| 型號： | DS17887-5IND+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 5V 8K NV RAM 24-EDIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 14 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出 |
| 存儲容量： | 8KB |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP 模塊（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-EDIP |
| 包裝： | 管件 |
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Bit 7: Interrupt Request Flag (IRQF). This bit is set to
1 when any of the following are true:
PF = PIE = 1
WF = WIE = 1
AF = AIE = 1
KF = KSE = 1
UF = UIE = 1
RF = RIE = 1
Any time the IRQF bit is 1, the IRQ pin is driven low.
Flag bits PF, AF, and UF are cleared after reading
Register C.
Bit 6: Periodic Interrupt Flag (PF). This is a read-only
bit that is set to 1 when an edge is detected on the
selected tap of the divider chain. The RS3–RS0 bits
establish the periodic rate. PF is set to 1 independent
of the state of the PIE bit. When both PF and PIE are 1s,
the IRQ signal is active and sets the IRQF bit. Reading
Register C clears this bit.
Bit 5: Alarm Interrupt Flag (AF). A 1 in this bit indicates
that the current time has matched the alarm time. If the
AIE bit is also 1, the IRQ pin goes low and a 1 appears in
the IRQF bit. Reading Register C clears this bit.
Bit 4: Update-Ended Interrupt Flag (UF). This bit is
set after each update cycle. When the UIE bit is set to
1, the 1 in UF causes the IRQF bit to be 1, which
asserts IRQ. Reading Register C clears this bit.
Bits 3 to 0: Unused. These unused bits always read 0
and cannot be written.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
____________________________________________________________________
17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IRQF
PF
AF
UF
0000
Register C (0Ch)
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT
00
00000
Register D (0Dh)
MSB
LSB
Register D (0Dh)
Bit 7: Valid RAM and Time (VRT). This bit indicates
the condition of the battery connected to the VBAT and
VBAUX pin. If either supply is above the internal voltage
threshold, VRTTRIP, the bit will be high. This bit is not
writeable and should always be a 1 when read. If a 0 is
ever present, an exhausted internal lithium energy
source is indicated and both the contents of the RTC
data and RAM data are questionable.
Bits 6 to 0: Unused. These bits cannot be written and,
when read, always read 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS17887-5IND+ | 功能描述:實(shí)時(shí)時(shí)鐘 3V/5V RTC RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS17H531D | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:3-PHASE STEPPING SYSTEMS |
| DS17H531S | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:3-PHASE STEPPING SYSTEMS |
| DS17H532D | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:3-PHASE STEPPING SYSTEMS |
| DS17H532S | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:3-PHASE STEPPING SYSTEMS |
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