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| 型號(hào)： | DS17485-5+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 4/31頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC 5V 4K NV RAM 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 16 |
| 類(lèi)型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出 |
| 存儲(chǔ)容量： | 4KB |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
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DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Power-Down/Power-Up
Considerations
The RTC function continues to operate, and all the
RAM, time, calendar, and alarm memory locations
remain nonvolatile regardless of the level of the VCC
input. VBAT or VBAUX must remain within the minimum
and maximum limits when VCC is not applied. When
VCC falls below VPF, the device inhibits all access,
putting the part into a low-power mode. When VCC is
applied and exceeds VPF (power-fail trip point), the
device becomes accessible after tREC, if the oscillator
is running and the oscillator countdown chain is not in
reset (Register A). This time period allows the system to
stabilize after power is applied. If the oscillator is not
enabled, the oscillator enable bit is enabled on power-
up, and the device becomes immediately accessible.
Power Control
The power control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The
device is fully accessible and data can be written and
read when VCC is greater than VPF. However, when
VCC falls below VPF, the device inhibits read and write
access. If VPF is less than VBAT, the device power is
switched from VCC to the higher of VBAT or VBAUX
when VCC drops below VPF. If VPF is greater than the
higher of VBAT or VBAUX, the device power is switched
from VCC to the higher of VBAT or VBAUX when VCC
drops below the higher backup source. The registers
are maintained from the VBAT or VBAUX source until
VCC is returned to nominal levels. After VCC returns
above VPF, read and write access is allowed after tREC.
Time, Calendar, and Alarm
Locations
The time and calendar information is obtained by read-
ing the appropriate register bytes. The time, calendar,
and alarm are set or initialized by writing the appropri-
ate register bytes. The contents of the 12 time, calen-
dar, and alarm bytes can be either binary or
binary-coded decimal (BCD) format. Tables 3A and 3B
show the BCD and binary formats of the 12 time, date,
and alarm registers, control registers A to D, plus the
two extended registers that reside in bank 1 only (bank
0 and bank 1 switching is explained later in this text).
The day-of-week register increments at midnight, incre-
menting from 1 through 7. The day-of-week register is
used by the daylight saving function, and so the value
1 is defined as Sunday. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including correction for leap years.
Before writing the internal time, calendar, and alarm
registers, the SET bit in Register B should be written to
logic 1 to prevent updates from occurring while access
is being attempted. In addition to writing the 12 time,
calendar, and alarm registers in a selected format
(binary or BCD), the data mode bit (DM) of Register B
must be set to the appropriate logic level. All 12 time,
calendar, and alarm bytes must use the same data
mode. The set bit in Register B should be cleared after
the data mode bit has been written to allow the real
time clock to update the time and calendar bytes. Once
initialized, the real time clock makes all updates in the
selected mode. The data mode cannot be changed
without reinitializing the 12 data bytes. Tables 3A and
3B show the BCD and binary formats of the 12 time,
calendar, and alarm locations.
The 24-12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected,
the high order bit of the hours byte represents PM when
it is logic 1. The time, calendar, and alarm bytes are
always accessible because they are double-buffered.
Once per second, the eight bytes are advanced by one
second and checked for an alarm condition.
If a read of the time and calendar data occurs during
an update, a problem exists where seconds, minutes,
hours, etc., may not correlate. The probability of read-
ing incorrect time and calendar data is low. Several
methods of avoiding any possible incorrect time and
calendar reads are covered later in this text.
Real-Time Clocks
12
____________________________________________________________________
Table 2. Power Control
SUPPLY CONDITION
READ/WRITE
ACCESS
POWERED BY
VCC < VPF, VCC <
(VBAT | VBAUX)
No
VBAT or VBAUX
VCC < VPF, VCC >
(VBAT | VBAUX)
No
VCC
VCC > VPF, VCC <
(VBAT | VBAUX)
Yes
VCC
VCC > VPF, VCC >
(VBAT | VBAUX)
Yes
VCC
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