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參數(shù)資料
型號: DS1746P-70IND+
廠商: Maxim Integrated Products
文件頁數(shù): 12/16頁
文件大?。?/td> 0K
描述: IC RTC RAM Y2K 5V 70NS 34-PCM
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
類型: 時鐘/日歷
特點: 閏年,NVSRAM,Y2K
存儲容量: 128KB
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 34-PowerCap? 模塊
供應商設備封裝: 34-PowerCap 模塊
包裝: 管件
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
5 of 16
Table 1. Truth Table
VCC
CE
OE
WE
MODE
DQ
POWER
VCC>VPF
VIH
X
Deselect
High-Z
Standby
VIL
X
VIL
Write
Data In
Active
VIL
VIH
Read
Data Out
Active
VIL
VIH
Read
High-Z
Active
VSO<VCC<VPF
X
Deselect
High-Z
CMOS Standby
VCC<VSO<VPF
X
Deselect
High-Z
Data-Retention Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates
to the device registers. The user can subsequently load correct date and time values into all eight registers,
followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings
into the clock, allowing timekeeping operations to resume from the new set point.
Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts
updates to the device registers. The user can subsequently read the date and time values from the eight
registers without those contents possibly changing during those I/O operations. A subsequent write cycle
of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the
previous set point.
The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a
write cycle to Control if either the W or R bits are being set to 1 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write
cycle to Control if the W bit is being cleared to 0 in that write operation.
The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write
cycle to Control if the R bit is being cleared to 0 in that write operation.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (see
Table 2). Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1746 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The
electrical environment also affects clock accuracy and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note
58.
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