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參數(shù)資料
| 型號： | DS1744WP-120IND |
| 英文描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 中文描述： | 千年蟲的，非易失時鐘存儲器 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 348K |
| 代理商： | DS1744WP-120IND |
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
5 of 18
Table 2.
Register Map
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION RANGE
7FFFF
7FFFE
7FFFD
7FFFC
7FFFB
7FFFA
7FFF9
7FFF8
10 Year
Year
Month
Date
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
X
BF
X
X
OSC
W
X
X
FT
X
X
10 Month
10 Date
X
X
X
Day
10 Hour
Hour
Minutes
Seconds
Century
10 Minutes
10 Seconds
10 Century
R
OSC
= Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
locations in the NV SRAM. Valid data is available at the DQ pins within t
AA
after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data is available at the latter of chip-enable access (t
CEA
) or at output-enable access
time (t
OEA
). The state of the DQ pins is controlled by CE and OE. If the outputs are activated before t
AA
,
the data lines are driven to an intermediate state until t
AA
. If the address inputs are changed while CE and
OE remain valid, output data remains valid for output-data hold time (t
OH
) but then goes indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CEare in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the OE signal is high during a write cycle. However, OE can be active provided that
care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on WE then
disables the output t
WEZ
after WE goes active.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1744WP-120IND+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1745Y-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1745Y-150-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1745Y-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1745Y-200-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
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