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參數(shù)資料
| 型號： | DS1743P-100 |
| 英文描述： | OSC 3.3V SMT 7X5 CMOS |
| 中文描述： | Y2KC非易失內(nèi)存時鐘 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 247K |
| 代理商： | DS1743P-100 |
DS1743/DS1743P
5 of 17
WRITING DATA TO RAM OR CLOCK
The DS1743 is in the write mode whenever
WE
, and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
, on
CE
. The addresses must be held valid throughout
the cycle.
CE
or
WE
must return inactive for a minimum of t
WR
prior to the initiation of another read or
write cycle. Data in must be valid t
DS
prior to the end of write and remain valid for t
DH
afterward. In a
typical application, the
OE
signal will be high during a write cycle. However,
OE
can be active provided
that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on
WE
will
then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when V
CC
is greater than V
PF.
However, when V
CC
is below the power fail point, V
PF
,
(point at which write protection occurs) the internal
clock registers and SRAM are blocked from any access. At this time(PowerCap only)the power fail reset
output signal (
RST) is driven active and will remain active until V
CC
returns to nominal levels. When V
CC
falls below the battery switch point V
SO
(battery supply level), device power is switched from the V
CC
pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels. The 3.3-volt device is fully accessible and data can be written or read only when V
CC
is
greater than V
PF.
When V
CC
falls below the power fail point, V
PF
,
access to the device is inhibited. At this
time the power fail reset output signal (RST) is driven active and will remain active until V
CC
returns to
nominal levels. If V
PF
is less than Vso
,
the device power is switched from V
CC
to the backup supply (V
BAT
)
when V
CC
drops below V
PF.
If V
PF
is greater than Vso, the device power is switched from V
CC
to the backup
supply (V
BAT)
when V
CC
drops below Vso. RTC operation and SRAM data are maintained from the battery
until V
CC
is returned to nominal levels. The RST(PowerCap only) signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down when
V
CC
is powered down.
BATTERY LONGEVITY
The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and
RAM data retention when the V
CC
supply is not present. The capability of this internal power supply is
sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25
°
C with the internal clock oscillator running in
the absence of V
CC
power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a level greater than
V
PF
, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1743 will be much longer than 10 years since no lithium battery energy is consumed when V
CC
is
present.
BATTERY MONITOR
The DS1743 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and should
always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both
the contents of the RTC and RAM are questionable.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1743P-70 | Y2KC Nonvolatile Timekeeping RAM |
| DS1743 | Y2KC Nonvolatile Timekeeping RAM |
| DS1743P | Y2KC Nonvolatile Timekeeping RAM |
| DS1744 | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| DS1744-70 | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1743P-100+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743P-100IND | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743P-100IND+ | 功能描述:實時時鐘 Timekeeping NV RAM RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743P-70 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1743P-70+ | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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