參數(shù)資料
型號: DS1743
英文描述: Y2KC Nonvolatile Timekeeping RAM
文件頁數(shù): 3/17頁
文件大小: 247K
代理商: DS1743
DS1743/DS1743P
3 of 17
DS1743 BLOCK DIAGRAM
Figure 1
DS1743 TRUTH TABLE
Table 1
V
CC
CE
V
IH
X
V
IL
V
IL
V
IL
X
X
CE2
X
V
IL
V
IH
V
IH
V
IH
X
X
OE
X
X
X
V
IL
V
IH
X
X
WE
X
X
V
IL
V
IH
V
IH
X
X
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
V
CC
>V
PF
V
SO
<V
CC
<V
PF
V
CC
<V
SO
<V
PF
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
OSC
bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,
CE
low,
OE
low,
WE
high, and address for seconds register remain valid and
stable).
相關PDF資料
PDF描述
DS1743P Y2KC Nonvolatile Timekeeping RAM
DS1744 Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744-70 Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744-70IND Y2K-Compliant, Nonvolatile Timekeeping RAMs
DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
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