參數(shù)資料
型號: DS1742
廠商: Maxim Integrated Products, Inc.
英文描述: Y2KC Nonvolatile Timekeeping RAM(Y2KC非易失性計時RAM)
文件頁數(shù): 3/13頁
文件大小: 95K
代理商: DS1742
DS1742
061998 3/13
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The clock oscillator may be stopped at any time. To in-
crease the shelf life, the oscillator can be turned off to
minimize current drain from the battery. The OSC bit is
the MSB (bit 7) of the seconds registers, see Table 2.
Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency
test bit. When the frequency test bit is set to logic “1” and
the oscillator is running, the LSB of the seconds register
will toggle at 512 Hz. When the seconds register is be-
ing read, the DQ0 line will toggle at the 512 Hz frequency
as long as conditions for access remain valid (i.e., CE
low, OE low, WE high, and address for seconds register
remain valid and stable).
CLOCK ACCURACY
The DS1742 is guaranteed to keep time accuracy to
within
±
1 minute per month at 25
°
C. The clock is cali-
brated at the factory by Dallas Semiconductor using
special calibration nonvolatile tuning elements. The
DS1742 does not require additional calibration and tem-
perature deviations will have a negligible effect in most
applications. For this reason, methods of field clock cal-
ibration are not available and not necessary.
DS1742 REGISTER MAP
Table 2
ADDRESS
DATA
FUNCTION/RANGE
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
7FF
10 YEAR
YEAR
YEAR
00–99
7FE
X
X
X
10 MO
MONTH
MONTH
01–12
7FD
X
X
10 DATE
DATE
DATE
01–31
7FC
BF
FT
X
X
X
DAY
DAY
01–07
7FB
X
X
10 HOUR
HOUR
HOUR
00–23
7FA
X
10 MINUTES
MINUTES
MINUTES
00–59
7F9
OSC
10 SECONDS
SECONDS
SECONDS
00–59
7F8
W
R
10 CENTURY
CENTURY
CENTURY
00–39
OSC = STOP BIT
W
= WRITE BIT
R
X
=
=
READ BIT
SEE NOTE BELOW
FT =
BF =
FREQUENCY TEST
BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output
enable) is low, WE (write enable) is high, and CE (chip
enable) is low. The device architecture allows ripple-
through access to any of the address locations in the NV
SRAM. Valid data will be available at the DQ pins within
t
AA
after the last address input is stable, providing that
the CE, and OE access times and states are satisfied. If
CE, or OE access times and states are not met, valid
data will be available at the latter of chip enable access
(t
CEA
) or at output enable access time (t
OEA
). The state
of the data input/output pins (DQ) is controlled by CE,
and OE. If the outputs are activated before t
AA
, the data
lines are driven to an intermediate state until t
AA
. If the
address inputs are changed while CE, and OE remain
valid, output data will remain valid for output data hold
time (t
OH
) but will then go indeterminate until the next
address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE, and CE
are in their active state. The start of a write is referenced
to the latter occurring transition of WE, on CE. The ad-
dresses must be held valid throughout the cycle. CE, or
WE must return inactive for a minimum of t
WR
prior to
the initiation of another read or write cycle. Data in must
be valid t
DS
prior to the end of write and remain valid for
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