The DS1742 is in the read mode whenever OE
參數(shù)資料
型號: DS1742-100
廠商: Maxim Integrated Products
文件頁數(shù): 14/17頁
文件大?。?/td> 0K
描述: IC RTC RAM Y2K 5V 100NS 24-EDIP
標準包裝: 14
類型: 時鐘/日歷
特點: 閏年,NVSRAM,Y2K
存儲容量: 2KB
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 24-DIP 模塊(0.600",15.24mm)
供應商設(shè)備封裝: 24-EDIP
包裝: 管件
DS1742
6 of 17
RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is
high, and CE (chip enable) is low. The device architecture allows ripple-through access to any
of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA
after the last address input is stable, providing that the CE and OE access times and states are
satisfied. If CE or OE access times and states are not met, valid data will be available at the
latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data
input/output pins (DQ) is controlled by CE , and OE . If the outputs are activated before tAA, the
data lines are driven to an intermediate state until tAA. If the address inputs are changed while
CE
and OE remain valid, output data will remain valid for output data hold time (tOH) but will then
go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever WE and CE are in their active state. The start of a
write is referenced to the latter occurring transition of WE on CE . The addresses must be held
valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the
initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and
remain valid for tDH afterward. In a typical application, the OE signal will be high during a write
cycle. However, OE can be active provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the data bus can become active with read
data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ
after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than
VPF. However, when VCC is below the power fail point, VPF, (point at which write protection
occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC
pin to the backup battery. RTC operation and SRAM data are maintained from the battery until
VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or
read only when VCC is greater than VPF. When VCC falls below the power fail point, VPF, access to
the device is inhibited. If VPF is less than Vso, the device power is switched from VCC to the
backup supply (VBAT) when VCC drops below VPF. If VPF is greater than Vso, the device power is
switched from VCC to the backup supply (VBAT) when VCC drops below Vso. RTC operation and
SRAM data are maintained from the battery until VCC is returned to nominal levels.
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DS1742-100IND 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
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DS1742-70 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS1742-70+ 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube