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參數資料
| 型號： | DS1689S |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 13/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC SER W/NV RAM CTRL 28-SOIC |
| 標準包裝： | 26 |
| 類型： | 時鐘/日歷 |
| 特點： | NVSRAM |
| 存儲容量： | 114B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | 并聯 |
| 電源電壓： | 2.7 V ~ 3.3 V，4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 管件 |
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DS1689/DS1693
20 of 36
applied, the on-chip logic always attempts to drive the
PWR pin active in response to the enabled
kickstart or wake-up condition. This is true even if
PWR was previously inactive as the result of power
being applied by some means other than wake-up or kickstart.
The system can be powered down under software control by setting the PAB bit to logic 1. This causes
the open-drain
PWR pin to be placed in a high-impedance state, as shown at the beginning of interval 4 in
the timing diagram. As VCC voltage decays, the IRQ output pin is placed in a high-impedance state when
VCC goes below VPF. If the system is to be again powered on in response to a wake-up or kickstart, then
both the WF and KF flags should be cleared and WIE and/or KSE should be enabled prior to setting the
PAB bit.
During interval 5, the system is fully powered down. Battery backup of the clock calendar and NV RAM
is in effect,
PWR and IRQ are tri-stated, and monitoring of wake-up and kickstart takes place.
RAM CLEAR
The DS1689/DS1693 provide a RAM clear function for the 114 bytes of user RAM. When enabled, this
function can be performed regardless of the condition of the VCC pin.
The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register
04BH). When this bit is set to logic 1, the 114 bytes of user RAM are cleared (all bits set to 1) when an
active-low transition is sensed on the
RCLR pin. This action has no effect on either the clock/calendar
settings or upon the contents of the external extended RAM. The RAM clear flag (RF, bank 1, register
04BH) is set when the RAM clear operation has been completed. If VCC is present at the time of the RAM
clear and RIE = 1, the
IRQ line is also driven low upon completion. The interrupt condition can be
cleared by writing a 0 to the RF bit. The
IRQ line then returns to its inactive high level, provided there are
no other pending interrupts. Once the
RCLR pin is activated, all read/write accesses are locked out for a
minimum recover time, specified as tREC in the Electrical Characteristics section.
When RCE is cleared to 0, the RAM clear function is disabled. The state of the
RCLR pin has no effect
on the contents of the user RAM, and transitions on the
RCLR pin have no effect on RF.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| DS1689S/R | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Serialized Real-Time Clocks with NV RAM Control |
| DS1689S/T | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3V/5V Serialized Real-Time Clocks with NV RAM Control |
| DS1689S/T&R | 制造商:Rochester Electronics LLC 功能描述: |
| DS1689S/T&R | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1689S/T&R/ | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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