參數(shù)資料
型號(hào): DS1685Q-3+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 32/34頁(yè)
文件大?。?/td> 0K
描述: IC RTC 3V 64-BIT Y2KC 28-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,NVSRAM,方波輸出,Y2K
存儲(chǔ)容量: 242B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 2.7 V ~ 3.7 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
DS1685/DS1687 3V/5V Real-Time Clocks
7 of 34
Table 1. Crystal Specifications*
8B
PARAMETER
9B
SYMBOL
MIN
TYP
MAX
UNITS
Nominal Frequency
fO
32.768
kHz
Series Resistance
ESR
50
k
Load Capacitance
CL
6, 12.5
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations
for Dallas Real-Time Clocks for additional specifications.
CLOCK ACCURACY
The accuracy of the clock is dependent on the accuracy of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is
added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator
circuit can result in the clock running fast. Figure 3 shows a typical PC board layout for isolation of the crystal and
oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for
detailed information.
The DS1685 can also be driven by an external 32.768 kHz oscillator. In this configuration, the X1 pin is connected
to the external oscillator signal and the X2 pin is floated. Refer to Application Note 58: Crystal Considerations with
Dallas Real-Time Clocks for detailed information about crystal selection and crystal layout.
Figure 2. Oscillator Circuit Showing Internal Bias Network
Figure 3. Typical Crystal Layout
Countdown
Chain
RTC
X1
X2
Crystal
CL1
CL2
RTC
Registers
Local ground plane (Layer 2)
crystal
X1
X2
GND
NOTE: AVOID ROUTING SIGNAL LINES IN
THE CROSSHATCHED AREA (UPPER
LEFT QUADRANT) OF THE PACKAGE
UNLESS THERE IS A GROUND PLANE
BETWEEN THE SIGNAL LINE AND THE
DEVICE PACKAGE.
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