參數(shù)資料
型號(hào)： DS14285
廠商： DALLAS SEMICONDUCTOR
元件分類(lèi)： XO, clock
英文描述： Real Time Clock with NV RAM Control(帶非易失性RAM控制的實(shí)時(shí)時(shí)鐘)
中文描述： 1 TIMER(S), REAL TIME CLOCK, PDIP24
封裝： DIP-24
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 170K
代理商： DS14285
DS14285/DS14287
022798 9/23
NONVOLATILE RAM
The 114 general purpose nonvolatile RAM bytes are not
dedicated to any special function within the
DS14285/DS14287. They can be used by the proces-
sor program as nonvolatile memory and are fully avail-
able during the update cycle.
The DS14285/DS14287 can also provide additional
nonvolatile RAM. This is accomplished through the use
of its internal lithium cell in the case of the DS14287 (or
the energy source connected to the V
BAT
pin in the case
of the DS14285) and battery–backup controller to make
a standard CMOS SRAM nonvolatile during power–fail
conditions. During power fail, the DS14285/DS14287
automatically write protects the external SRAM and pro-
vides a V
CC
output sourced from the internal lithium cell.
The interface between the DS14285/DS14287 and an
external SRAM is illustrated in Figure 2.
INTERRUPTS
The RTC plus RAM includes three separate, fully auto-
matic sources of interrupt for a processor. The alarm
interrupt can be programmed to occur at rates from
once per second to once per day. The periodic interrupt
can be selected for rates from 500 ms to 122
μ
s. The
update-ended interrupt can be used to indicate to the
program that an update cycle is complete. Each of
these independent interrupt conditions is described in
greater detail in other sections of this text.
The processor program can select which interrupts, if
any, are going to be used. Three bits in Register B
enable the interrupts. Writing a logic 1 to an interrupt-
enable bit permits that interrupt to be initiated when the
event occurs. A zero in an interrupt-enable bit prohibits
the IRQ pin from being asserted from that interrupt
condition. If an interrupt flag is already set when an
interrupt is enabled, IRQ is immediately set at an active
level, although the interrupt initiating the event may
have occurred much earlier. As a result, there are cases
where the program should clear such earlier initiated
interrupts before first enabling new interrupts.
When an interrupt event occurs, the relating flag bit is
set to logic 1 in Register C. These flag bits are set inde-
pendent of the state of the corresponding enable bit in
Register B. The flag bit can be used in a polling mode
without enabling the corresponding enable bits. The
interrupt flag bit is a status bit which software can
interrogate as necessary. When a flag is set, an indica-
tion is given to software that an interrupt event has
occurred since the flag bit was last read; however, care
should be taken when using the flag bits as they are
cleared each time Register C is read. Double latching is
included with Register C so that bits which are set
remain stable throughout the read cycle. All bits which
are set (high) are cleared when read and new interrupts
which are pending during the read cycle are held until
after the cycle is completed. One, two, or three bits can
be set when reading Register C. Each utilized flag bit
should be examined when read to ensure that no inter-
rupts a re lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt flag bit is set and the corre-
sponding interrupt enable bit is also set, the IRQ pin is
asserted low. IRQ is asserted as long as at least one of
the three interrupt sources has its flag and enable bits
both set. The IRQF bit in Register C is a one whenever
the IRQ pin is being driven low. Determination that the
RTC initiated an interrupt is accomplished by reading
Register C. A logic one in bit 7 (IRQF bit) indicates that
one or more interrupts have been initiated by the
DS14285/DS14287. The act of reading Register C
clears all active flag bits and the IRQF bit.
OSCILLATOR CONTROL BITS
When the DS14287 is shipped from the factory, the
internal oscillator is turned off. This feature prevents the
lithium energy cell from being used until it is installed in a
system. A pattern of 010 in bits 4 through 6 of Register A
will turn the oscillator on and enable the countdown
chain. A pattern of 11X will turn the oscillator on, but
holds the countdown chain of the oscillator in reset. All
other combinations of bits 4 through 6 keep the oscilla-
tor off.
SQUARE WAVE OUTPUT SELECTION
Thirteen of the 15 divider taps are made available to a
1–of–15 selector, as shown in the block diagram of Fig-
ure 1. The first purpose of selecting a divider tap is to
generate a square wave output signal on the SQW pin.
The RS0-RS3 bits in Register A establish the square
wave output frequency. These frequencies are listed in
Table 1. The SQW frequency selection shares its
1–of–15 selector with the periodic interrupt generator.
Once the frequency is selected, the output of the SQW
pin can be turned on and off under program control with
the square wave enable bit (SQWE).
相關(guān)PDF資料
PDF描述
DS14287 Real Time Clock with NV RAM Control(帶非易失性RAM控制的實(shí)時(shí)時(shí)鐘)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS14285_05 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:Real-Time Clock with NV RAM
DS14285+ 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS14285-DS14287 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:Real Time Clock with NV RAM Control
DS14285N 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS14285N+ 功能描述:實(shí)時(shí)時(shí)鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
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