參數(shù)資料
型號: DS1410E
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Microprocessor IC:Other
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT
文件頁數(shù): 5/9頁
文件大?。?/td> 386K
代理商: DS1410E
DS1410E
5 of 7
021798
HOST INTERFACE TIMING DIAGRAMS Figure 3 (cont’d)
tPDH = 2 μs (TYPICAL)
tBLR = 960 μs (MINIMUM) (OD = 0
tBLB = 96 μs (MINIMUM) (OD = 1)
1- WIRE RESET
PIN
I/O
DESCRIPTION
Input pin
14 ( EN I)
I
Chip enable, driven low to begin 1-Wire I/O.
Input pin 11
(O1/ BSY1)
O
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of I1 after time slot has finished. (O1/ BSY1) will go low after D/ CLK goes low
if sample of I/O communication was low. Returns to state I1 when ENI goes
back high (see Figure).
Input pin 13
(O2/ BSY2 )
O
Driven low during time slot (to indicate a DS1481 busy condition). Set to state
of 12 after time slot has finished. O2/ BSY2 will go low after D/ CLK goes low
if sample of I/O communication was low. Returns to state of 12 when ENI
goes back high (see Figure).
Input pin 2
(D/ CLK )
I
Data/Clock pin. Used to specify type of time slot before communication
begins. After the time slot has been completed this pin is driven low in order to
solicit the result of the time slot.
Input pin 3
( RES )
I
Set low (before ENI is driven low) to specify that a reset pulse should be
generated on the I/O pin.
Output Pin 11
(I1)
I
Can be connected to the O1/ BSY1of another DS1481. May also be connected
to a parallel port printer’s BUSY signal. Internally pulled high via a weak
resistor.
Output Pin 13
(I2)
I
Can be connected to the O2/ BSY2 of another DS1481. Can also be connected
to a parallel port printer SELECT OUT signal. Internally pulled high via a
weak resistor
Output Pin 14
( ENO )
O
Set to ENI if not the last part on port. Open drain output with weak internal
pullup resistor.
I/O
1-Wire I/O line. Bi-directional line with open drain output.
Not
Recommended
for
New
Design
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