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參數(shù)資料
| 型號： | DS138632-120 |
| 英文描述： | RAMified Watchdog Timekeeper |
| 中文描述： | 網(wǎng)狀看門狗計時 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 263K |
| 代理商： | DS138632-120 |
DS1386/1386P
9 of 20
TIME OF DAY ALARM MASK BITS Figure 3
REGISTER
(3) MINUTES
(5) HOURS
(7) DAYS
1
ALARM ONCE PER MINUTE
0
1
ALARM WHEN MINUTES MATCH
0
1
ALARM WHEN HOURS AND MINUTES
MATCH
0
ALARM WHEN HOURS, MINUTES AND
DAYS MATCH
NOTE:
Any other bit combinations of mask bit settings produce illogical operation.
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
TE - Bit 7 Transfer Enable-This bit when set to a logic 0 will disable the transfer of data between internal
and external clock registers. The contents in the external clock registers are now frozen and reads or
writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
IPSW - Bit 6 Interrupt Switch-When set to a logic 1, INTA is the Time of Day Alarm and INTB/( INTB )
is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the watchdog
alarm output and INTB/( INTB ) is the time of day alarm output.
IBH/LO - Bit 5 Interrupt B Sink or Source Current-When this bit is set to a logic 1 and VCC is applied,
INTB/( INTB ) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTB
will sink current (see DC characteristics IOL).
PU/LVL - Bit 4 Interrupt Pulse Mode or Level Mode - This bit determines whether both interrupts will
output a pulse or level signal. When set to a logic 0, INTA and INTB/( INTB ) will be in the level mode.
When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of
3 ms and then release. INTB/( INTB ) will either sink or source current, depending on the condition of
Bit 5, for a minimum of 3 ms and then release. INTB will only source current when there is a voltage
present on VCC.
WAM - Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the watchdog interrupt output
will be activated. The activated state is determined by bits 1,4,5, and 6 of the COMMAND REGISTER.
When this bit is set to a logic 1, the watchdog interrupt output is deactivated.
TDM - Bit 2 Time of Day Alarm Mask - When this bit is set to a logic 0, the time of day alarm interrupt
output will be activated. The activated state is determined by bits 0,4,5, and 6 of the COMMAND
REGISTER. When this bit is set to a logic 1, the time of day alarm interrupt output is deactivated.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1386-32-120+ | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1386-8-120 | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1386-8-120+ | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1386-8-150 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS1386-8K | 制造商:Maxim Integrated Products 功能描述: |
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