參數(shù)資料
型號: DS12885Q+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 19/22頁
文件大?。?/td> 0K
描述: IC RTC W/RAM 128 BYTE 28-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 時鐘/日歷
特點(diǎn): 警報(bào)器,夏令時,閏年,NVSRAM,方波輸出
存儲容量: 114B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 4 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
6
_____________________________________________________________________
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
tRPU
20
200
ms
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tF
300
s
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tR
0s
CAPACITANCE
(TA = +25°C) (Note 9)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitance on All Input Pins
Except X1 and X2
CIN
5pF
Capacitance on IRQ, SQW, and
DQ Pins
CIO
7pF
DATA RETENTION
(TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Expected Data Retention
tDR
10
years
AC TEST CONDITIONS
PARAMETER
TEST CONDITIONS
Input Pulse Levels
0 to 3.0V
Output Load Including Scope and Jig
50pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels
Input/Output: VIL maximum and VIH minimum
Input-Pulse Rise and Fall Times
5ns
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1:
RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage.
Note 2:
Limits at -40°C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
All outputs are open.
Note 5:
Specified with CS = DS = R/W = RESET = VCC; MOT, AS, AD0–AD7 = 0; VBACKUP open.
Note 6:
Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state.
Note 7:
The MOT pin has an internal 20k
Ω pulldown.
Note 8:
Measured with a 32.768kHz crystal attached to X1 and X2.
Note 9:
Guaranteed by design. Not production tested.
Note 10: Measured with a 50pF capacitance load.
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