IH or VIL
參數(shù)資料
型號(hào): DS1286I
廠商: Maxim Integrated Products
文件頁數(shù): 6/18頁
文件大小: 0K
描述: IC TIMEKEEPER WATCHDOG 28-EDIP
標(biāo)準(zhǔn)包裝: 12
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,方波輸出,SRAM,監(jiān)視計(jì)時(shí)器
存儲(chǔ)容量: 50B
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.4 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 28-DIP 模塊(0.61",15.49mm)23 引線
供應(yīng)商設(shè)備封裝: 28-EDIP
包裝: 管件
DS1284/DS1286
14 of 18
NOTES:
1.
WE is high for a read cycle.
2.
OE = V
IH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going
low to the earlier of
CE or WE going high.
4. tDS or tDH are measured from the earlier of CE or WE going high.
5. tDH is measured from WE going high. If CE is used to terminate the write cycle, then tDH = 20ns.
6. If the
CE low transition occurs simultaneously with or later than the WE low transition in write cycle
1, the output buffers remain in a high-impedance state during this period.
7. If the
CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If
WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1284/DS1286 is marked with a four-digit date code AABB. AA designates the year of
manufacture. BB designates the week of manufacture. The expected tDR is defined as starting at the
date of manufacture.
10. All voltages are referenced to ground.
11. Applies to both interrupt pins when the alarms are set to pulse.
12. Interrupt output occurs within 100ns on the alarm condition existing.
13.
RTC modules can be successfully processed through conventional wave-soldering techniques as long
as temperature exposure to the lithium energy source contained within does not exceed +85°C.
However, post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic
vibrations are not used to prevent crystal damage.
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 PDIP
P28+9
28 PLCC
Q28+11
28 EDIP
MDP28+1
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