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  • 參數資料
    型號: DS1267-100
    元件分類: 數字電位計
    英文描述: Dual Digital Potentiometer Chip
    中文描述: 雙數字電位器芯片
    文件頁數: 6/12頁
    文件大?。?/td> 312K
    代理商: DS1267-100
    DS1267
    6 of 12
    102199
    LINEARITY MEASUREMENT CONFIGURATION
    Figure 5
    NOTE:
    In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI error.
    DS1267 ABSOLUTE AND RELATIVE LINEARITY
    Figure 6
    TYPICAL APPLICATION CONFIGURATIONS
    Figures 7 and 8 show two typical application configurations for theDS1267. By connecting the wiper
    terminal of the part to a high-impedance load, the effects of the wiper resistance is minimized, since the
    wiper resistance can vary from 400 to 1000ohms depending on wiper voltage. Figure 7 presents the
    device connected in an inverting variable gain amplifier. The gain of the circuit on Figure 7 is given by
    the following equation:
    Av = -n/(255-n); where n = 0 to 255
    Figure 8 shows the device operating in a fixed gain attenuator where the potentiometer is used to
    attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper
    resistance to minimize its effect on circuit gain.
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    相關代理商/技術參數
    參數描述
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