- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9324 > DS1248YP-70 (Maxim Integrated Products)IC NVSRAM 1MBIT 70NS 34PCM PDF資料下載
參數(shù)資料
| 型號： | DS1248YP-70 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 1MBIT 70NS 34PCM |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 類型： | Phantom 計時芯片 |
| 特點： | NVSRAM |
| 存儲容量： | 128KB |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 34-PowerCap? 模塊 |
| 供應商設備封裝： | 34-PowerCap 模塊 |
| 包裝： | 管件 |
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
5 of 19
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the
CE
and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer to
the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE
and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the phantom
clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles
generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The
preferred
way
to
manage
this
requirement
is
to
set
aside
just
one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is
compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next
location of the comparison register and awaits the next write cycle. If a match is not found, the pointer
does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during
pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and
data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom
clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin.
Cycles to other locations outside the memory block can be interleaved with CE cycles without
interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCP4331T-104E/ST | IC DGTL POT QUAD 100K 20TSSOP |
| MCP4331T-104E/ML | IC DGTL POT QUAD 100K 20QFN |
| DS1744W-120IND | IC RTC RAM Y2K 3.3V 120NS 28EDIP |
| DS1386-8-120 | IC TIMEKEEPER RAM 64K 32-EDIP |
| DS1556P-70 | IC RTC RAM Y2K 5V 70NS 34-PCM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1248YP-70+ | 功能描述:實時時鐘 1024k NV SRAM w/Phantom Clock RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1248YP70IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1024k NV SRAM with Phantom Clock |
| DS1249AB | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB100 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249AB-100 | 功能描述:NVRAM 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。