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參數(shù)資料
| 型號(hào)： | DS1245ABP-70-IND |
| 英文描述： | GT 31C 1#4,2#8,14#12,14#16 SKT |
| 中文描述： | 1024k非易失SRAM |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 221K |
| 代理商： | DS1245ABP-70-IND |
DS1245Y/AB
8 of 12
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
t
PD
t
F
t
R
t
REC
MIN
0
300
300
2
TYP
MAX
UNITS
μ
s
μ
s
μ
s
ms
NOTES
11
CE
,
WE
at V
IH
before Power-Down
V
CC
slew from V
TP
to 0V (
CE
at V
IH
)
V
CC
slew from 0V to V
TP
(
CE
at V
IH
)
CE
,
WE
at V
IH
after Power-Up
125
(t
A
=25
°
C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high impedance state.
3.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4.
t
DH
, t
DS
are measured from the earlier of
CE
or
WE
going high.
5.
These parameters are sampled with a 5 pF load and are not 100% tested.
6.
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high impedance state during this period.
7.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high impedance state during this period.
8.
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high impedance state during this period.
9.
Each DS1245 has a built-in switch that disconnects the lithium source until V
CC
is first applied by the
user. The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the time
power is first applied by the user.
10.
All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0
°
C to 70
°
C. For industrial products (IND), this range is -40
°
C to
+85
°
C.
11.
In a power-down condition the voltage on any pin may not exceed the voltage on V
CC
.
12.
t
WR1
and t
DH1
are measured from
WE
going high.
13.
t
WR2
and t
DH2
are measured from
CE
going high.
14.
DS1245 DIP modules are recognized by Underwriters Laboratory (U.L.
) under file E99151.
DS1245 PowerCap modules are pending U.L. review. Contact the factory for status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1245ABP-70IND+ | 功能描述:NVRAM 1024K SRAM Nonvolatile RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1245ABP-85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
| DS1245ABP-85-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1024k Nonvolatile SRAM |
| DS1245BL-100 | 功能描述:IC NVSRAM 1MBIT 100NS 34LPM RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF) |
| DS1245BL-100-IND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (Battery Based) |
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