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參數(shù)資料
| 型號： | DS1225Y-150 |
| 元件分類： | DRAM |
| 英文描述： | 64K Nonvolatile SRAM |
| 中文描述： | 64K的非易失SRAM |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 147K |
| 代理商： | DS1225Y-150 |
DS1225AB/AD
2 of 10
READ MODE
The DS1225AB and DS1225AD execute a read cycle whenever WE(Write Enable) is inactive (high) and
CE(Chip Enable) and OE(Output Enable) are active (low). The unique address specified by the 13
address inputs (A
0
-A
12
) defines which of the 8192 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within t
ACC
(Access Time) after the last address input signal is
stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active
(low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the
start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initiated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and
OE active) then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1225AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1225AD provides full-functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As V
CC
falls below approximately 3.0 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1225AB and 4.5 volts for the
DS1225AD.
FRESHNESS SEAL
Each DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level of greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1225Y-150+ | 功能描述:NVRAM 64k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1225Y-150IND | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1225Y-150-IND | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:64K Nonvolatile SRAM |
| DS1225Y-150IND+ | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1225Y-170 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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