參數(shù)資料
型號(hào): DS1220AD-120-IND
英文描述: 16k Nonvolatile SRAM
中文描述: 16K的非易失SRAM
文件頁(yè)數(shù): 7/9頁(yè)
文件大?。?/td> 136K
代理商: DS1220AD-120-IND
DS1220AB/AD
7 of 9
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
(t
A
: See Note 10)
MAX
UNITS
μ
s
μ
s
μ
s
125
ms
SYMBOL
t
PD
t
F
t
R
t
REC
MIN
0
300
300
2
TYP
NOTES
11
CE
at
V
IH
before Power-Down
V
CC
slew from V
TP
to 0v
V
CC
slew from 0
V
to V
TP
CE
at V
IH
after Power-Up
(T
A
=25°C)
UNITS
years
PARAMETER
Expected Data Retention Time
SYMBOL
t
DR
MIN
10
TYP
MAX
NOTES
9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when device is in the
battery backup mode.
NOTES:
1.
WEis high for a read cycle.
2.
OE= V
IH
or V
IL
. If OE= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3.
t
WP
is specified as the logical AND of CEand WE. t
WP
is measured from the latter of CE or CE
going low to the earlier of CE or WE going high.
4.
t
DS
is measured from the earlier of CE or WE going high.
5.
These parameters are sampled with a 5 pF load and are not 100% tested.
6.
If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
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