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參數(shù)資料
| 型號： | DS1217M3-25 |
| 英文描述： | Nonvolatile Read/Write Cartridge |
| 中文描述： | 非易失讀/寫墨盒 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 83K |
| 代理商： | DS1217M3-25 |
DS1217M
030598 2/8
READ MODE
The DS1217M executes a read cycle whenever WE
(write enable) is inactive (high) and CE (cartridge en-
able) is active (low). The unique address specified by
the address inputs (A0-A14) defines which byte of data
is to be accessed. Valid data will be available to the eight
data I/O pins within t
ACC
(access time) after the last ad-
dress input signal is stable, providing that CE (cartridge
enable) and OE (output enable) access times are also
satisfied. If OE and CE times are not satisfied, then data
access must be measured from the late occurring signal
(CE or OE) and the limiting parameter is either t
CO
for
CE or t
OE
for OE rather than address access. Read
cycles can only occur when V
CC
is greater than 4.5
volts. When V
CC
is less than 4.5 volts, the memory is in-
hibited and all accesses are ignored.
WRITE MODE
The DS1217M is in the write mode whenever both the
WE and CE signals are in the active (low) state after ad-
dress inputs are stable. The last occurring falling edge
of either CE or WE will determine the start of the write
cycle. The write cycle is terminated by the first rising
edge of either CE or WE. All address inputs must be
kept valid throughout the write cycle. WE must return to
the high state for a minimum recovery time (t
WR
) before
another cycle can be initiated.The OE control signal
should be kept inactive (high) during write cycles to
avoid bus contention. However, if the output bus has
been enabled (CE and OE active) then WE will disable
the outputs in t
ODW
from its falling edge. Write cycles
can only occur when V
CC
is greater than 4.5 volts. When
V
CC
is less than 4.5 volts, the memory is write-pro-
tected.
DATA RETENTION MODE
The Nonvolatile Cartridge provides full functional capa-
bility for V
CC
greater than 4.5 volts and guarantees write
protection for V
CC
less than 4.5 volts. Data is main-
tained in the absence of V
CC
without any additional sup-
port circuitry. The DS1217M constantly monitors V
CC
.
Should the supply voltage decay, the RAM is automati-
cally write-protected below 4.5 volts. As V
CC
falls below
approximately 3.0 volts, the power switching circuit con-
nects a lithium energy source to RAM to retain data.
During power-up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects the exter-
nal V
CC
to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
CC
exceeds 4.5 volts.
The DS1217M checks battery status to warn of potential
data loss. Each time that V
CC
power is restored to the
cartridge the battery voltage is checked with a precision
comparator. If the battery supply is less than 2.0 volts,
the second memory cycle is inhibited. Battery status
can, therefore, be determined by performing a read
cycle after power-up to any location in memory, record-
ing that memory location content. A subsequent write
cycle can then be executed to the same memory loca-
tion, altering data. If the next read cycle fails to verify the
written data, the contents of the memory are question-
able.
In many applications, data integrity is paramount. The
cartridge thus has redundant batteries and an internal
isolation switch which provides for the connection of two
batteries. During battery backup time, the battery with
the highest voltage is selected for use. If one battery
fails, the other will automatically take over. The switch
between batteries is transparent to the user. A battery
status warning will occur only if both batteries are less
than 2.0 volts.
BANK SWITCHING
Bank switching is accomplished via address lines A8,
A9, A10, and A11. Initially, on power-up all banks are de-
selected so that multiple cartridges can reside on a com-
mon bus. Bank switching requires that a predefined pat-
tern of 64 bits is matched by sequencing 4 address
inputs (A8 through A11) 16 times while ignoring all other
address inputs. Prior to entering the 64-bit pattern which
will set the band switch, a read cycle of 1111 (address
inputs A8 through A11) must be executed to guarantee
that pattern entry starts with the first set of 3 bits. Each
set of address inputs is entered into the DS1217M by
executing read cycles.The first eleven cycles must
match the exact bit pattern as shown in Table 2. The last
five cycles must match the exact bit pattern for address-
es A9, A10, and A11. However, address line 8 defines
which of the 16 banks is to be enabled, or all banks are
deselected, as per Table 3. Switching from one bank to
another occurs as the last of the 16 read cycles is com-
pleted. A single bank is selected at any one time. A se-
lected bank will remain active until a new bank is se-
lected, all banks are deselected, or until power is lost.
(See DS1222 BankSwitch Chip data sheet for more de-
tail.)
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參數(shù)描述 |
|---|---|
| DS1217M-4-25 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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