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參數(shù)資料
| 型號： | DS1216F |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP32 |
| 封裝： | 0.600 INCH, DIP-32 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 122K |
| 代理商： | DS1216F |
DS1216E/F
2 of 10
DESCRIPTION
The DS1216 SmartWatch/ROM 64/256k 1M is 600 mil–wide DIP socket with a built–in CMOS
timekeeper function and an embedded lithium energy source to maintain time and date. The DS1216
accepts any 28-or 32 pin bytewide ROM or volatile RAM. A key feature of the SmartWatch is that the
timekeeper function remains transparent to the memory device placed above. The SmartWatch monitors
VCC for an out–of–tolerance condition. When such a condition occurs, an internal lithium energy source
is automatically switched on to prevent loss of watch data.
Using the SmartWatch saves PC board space since the combination of the SmartWatch and the mated
memory device takes up no more area than the memory alone. The SmartWatch uses signals RST , A2,
A0, DQ0, CE , and OE for timekeeper control. All pins pass through to the socket receptacle except for
pin 20 for DS1216E or 22 for DS1216F ( CE ), which is inhibited during the transfer of time information.
The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, date, month, and year information. The date at the end of the month is automatically adjusted
for months with fewer than 31 days, including correction for leap years. The SmartWatch operates in
either 24–hour or 12–hour format with an AM/PM indicator.
OPERATION
A highly structured sequence of 64 cycles is used to gain access to time information and temporarily
disconnects the mated memory from the system bus. Information transfer into and out of the SmartWatch
is achieved by using address bits A0 and A2, control signals OE and CE , and data I/O line DQ0. All
SmartWatch data transfers are accomplished by executing read cycles to the mated memory address
space. Write and read functions are determined by the level of address bit A2. When address bit A2 is
low, a write cycle is enabled and data must be input on address bit A0. When address bit A2 is high, a
read cycle is enabled and data is output on data I/O line DQ0. Either control signal ( OE or CE ) must
transition low to begin and high to end memory cycles that are directed to the SmartWatch. However,
both control signals must be in an active state during a memory cycle.
Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the
proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior
to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read
cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition
starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of
the 64–bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above, until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is
enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will
cause the SmartWatch to either receive data on Data In (A0) or transmit data on Data Out (DQ0),
depending on the level of
/WRITE
READ
(A2). Cycles to other locations outside the memory block can be
interleaved with CE and OE cycles without interrupting the pattern recognition sequence or data transfer
sequence to the SmartWatch.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1220AB-150 | 2K X 8 NON-VOLATILE SRAM MODULE, 150 ns, PDIP24 |
| DS1220AB-100 | 2K X 8 NON-VOLATILE SRAM MODULE, 100 ns, PDIP24 |
| DS1220AB-120 | 2K X 8 NON-VOLATILE SRAM MODULE, 120 ns, PDIP24 |
| DS1220AD-100 | 2K X 8 NON-VOLATILE SRAM MODULE, 100 ns, PDIP24 |
| DS1220AD-120 | 2K X 8 NON-VOLATILE SRAM MODULE, 120 ns, DMA24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1216F-3 | 功能描述:IC SMART/ROM 3V 64/256/1M 32DIP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| DS1216H | 功能描述:存儲器控制器 SmartWatch RAM RoHS:否 制造商:Maxim Integrated |
| DS1216MP000 | 制造商:Thomas & Betts 功能描述:100A,PLG,2P3W,MG,216,208V |
| DS1216MR000 | 制造商:Thomas & Betts 功能描述:100A,NLT,2P3W,MG,216,208V |
| DS1216MRA00 | 制造商:Thomas & Betts 功能描述:100A,NLT,2P3W,MG,AGL,208V |
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