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參數(shù)資料
| 型號(hào)： | DS1215 |
| 英文描述： | Phantom Time Chip |
| 中文描述： | 幻影時(shí)鐘芯片 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | DS1215 |
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DS1215
032697 2/15
OPERATION
The block diagram of Figure 1 illustrates the main ele-
ments of the Time Chip. Communication with the Time
Chip is established by pattern recognition of a serial bit
stream of 64 bits which must be matched by executing
64 consecutive write cycles containing the proper data
on data in (D). All accesses which occur prior to recog-
nition of the 64-bit pattern are directed to memory via the
chip enable output pin (CEO).
After recognition is established, the next 64 read or write
cycles either extract or update data in the Time Chip and
CEO remains high during this time, disabling the con-
nected memory.
Data transfer to and from the timekeeping function is ac-
complished with a serial bit stream under control of chip
enable input (CEI), output enable (OE), and write en-
able (WE). Initially, a read cycle using the CEI and OE
control of the Time Chip starts the pattern recognition
sequence by moving a pointer to the first bit of the 64 bit
comparison register. Next, 64 consecutive write cycles
are executed using the CEI and WE control of the Time
Chip. These 64 write cycles are used only to gain ac-
cess to the Time Chip.
TIMING BLOCK DIAGRAM
Figure 1
CLOCK/CALENDAR LOGIC
UPDATE
TIMEKEEPING REGISTER
COMPARISON REGISTER
INTERNAL V
CC
V
CCO
V
CCI
X
1
X
2
D
Q
DATA
POWER-FAIL
WRITE
READ
CEO
ROM/RAM
BAT
1
BAT
2
32.768 kHz
CEI
OE
WE
RST
CONTROL
LOGIC
ACCESS
ENABLE
SEQUENCE
DETECTOR
I/O BUFFERS
POWER–FAIL
DETECT
LOGIC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS1215G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| DS1215GN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| DS-1215ZJ | 制造商:Hikvision USA 功能描述:Camera Pole Mount Plate7.64In X 4.61In X 3.94In 制造商:HIKVISION 功能描述:CAMERA POLE MOUNT PLATE 7.64IN X 4.61IN X 3.94IN |
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| DS1216B | 功能描述:存儲(chǔ)器控制器 SmartWatch RAM RoHS:否 制造商:Maxim Integrated |
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