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參數(shù)資料
| 型號(hào)： | DS1110LE-400+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 10TAP 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 標(biāo)片/步級(jí)數(shù)： | 10 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 40ns |
| 接頭增量： | 40ns |
| 可用的總延遲： | 400ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
DS1110L
3V 10-Tap Silicon Delay Line
_____________________________________________________________________
3
Note 1: All voltages are referenced to ground.
Note 2: Measured with outputs open.
Note 3: Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and trailing edges.
Note 4: Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to
3.6V range.
Note 5: Intermediate delay values are available on a custom basis.
Note 6: See Test Conditions section.
Note 7: All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other
taps also slow down; tap 3 can never be faster than tap 2.
Note 8: Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.).
Note 9: For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.
CAPACITANCE
(TA = +25°C.)
Typical Operating Characteristics
(VCC = 3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
CIN
510
pF
-2
-1
0
1
2
3
4
-3
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-250
DS1110L
toc04
TEMPERATURE (
°C)
CHANGE
IN
DELAY
(%)
60
35
10
-15
-40
85
RISING EDGE
FALLING EDGE
CHANGE IN DELAY (%) vs. TEMPERATURE
DS1110L-500
DS1110L
toc03
TEMPERATURE (
°C)
CHANGE
IN
DELAY
(%)
60
35
10
-15
-4
-3
-2
-1
0
1
2
3
4
5
6
-5
-40
85
RISING EDGE
FALLING EDGE
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
-0.4
DELAY CHANGE (%)
vs. VCC DS1110L-250
DS1110L
toc02
VCC (V)
CHANGE
IN
DELAY
(%)
3.3
3.0
2.7
3.6
RAISING EDGE
FALLING EDGE
DELAY CHANGE (%)
vs. VCC DS1110L-500
DS1110L
toc01
VCC (V)
CHANGE
IN
DELAY
(%)
3.3
3.0
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
-0.35
2.7
3.6
RAISING EDGE
FALLING EDGE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1110LE-400+ | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-450 | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-450+ | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-50 | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-50+ | 功能描述:延遲線/計(jì)時(shí)元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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