- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9267 > DS1110LE-200+ (Maxim Integrated Products)IC DELAY LINE 10TAP 14-TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | DS1110LE-200+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 10TAP 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 標(biāo)片/步級(jí)數(shù)： | 10 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 20ns |
| 接頭增量： | 20ns |
| 可用的總延遲： | 200ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
DS1110L
Terminology
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following pulse.
tWI (Pulse Width): The elapsed time on the pulse
between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the
trailing edge and the 1.5V point on the leading edge.
tRISE (Input Rise Time): The elapsed time between the
20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the
80% and the 20% point on the trailing edge of the input
pulse.
tPLH (Time Delay Rising): The elapsed time between
the 1.5V point on the leading edge of the input pulse
and the 1.5V point on the leading edge of any tap out-
put pulse.
tPHL (Time Delay, Falling): The elapsed time between
the 1.5V point on the trailing edge of the input pulse
and the 1.5V point on the trailing edge of any tap out-
put pulse.
Test Setup Description
Figure 3 illustrates the hardware configuration used for
measuring the timing parameters on the DS1110L. A
precision pulse generator under software control pro-
duces the input waveform. Time delays are measured
by a time interval counter (20ps resolution) connected
3V 10-Tap Silicon Delay Line
6
______________________________________________________________________
PULSE
GENERATOR
TIME
INTERVAL
COUNTER
VHF SWITCH
CONTROL UNIT
STOP
DEVICE UNDER TEST
Z0 = 50
START
Figure 3. Test Circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J6Y-MZ | CONVERTER MOD DC/DC 3.3V 16.5W |
| DS1110LE-175+ | IC DELAY LINE 10TAP 14-TSSOP |
| VE-J6X-MZ | CONVERTER MOD DC/DC 5.2V 25W |
| VE-BTN-MW-B1 | CONVERTER MOD DC/DC 18.5V 100W |
| DS1110LE-150+ | IC DELAY LINE 10TAP 14-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1110LE-200+ | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-200-W | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-250 | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-250+ | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1110LE-300 | 功能描述:延遲線/計(jì)時(shí)元素 3V 10-Tap Silicon Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。