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參數(shù)資料
| 型號： | DS1100U-150/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 5TAP 150NS 8-USOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 3,000 |
| 標片/步級數(shù)： | 5 |
| 功能： | 不可編程 |
| 延遲到第一抽頭： | 30ns |
| 接頭增量： | 30ns |
| 可用的總延遲： | 150ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1100
4 of 7
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100.
The input waveform is produced by a precision-pulse generator under software control. Time delays are
measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap
is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT
Ambient Temperature:
+25°C
±3°C
Supply Voltage (VCC):
5.0V
±0.1V
Input Pulse:
High = 3.0V
±0.1V
Low = 0.0V
±0.1V
Source Impedance:
50
max
Rise and Fall Time:
3.0ns max (measured between 0.6V and 2.4V)
Pulse Width:
500ns (1μs for -500 version)
Period:
1μs (2μs for -500 version)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
Note: Above conditions are for test only and do not restrict the operation of the device under other
data sheet conditions.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1100U175 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| DS1100U-175 | 功能描述:延遲線/計時元素 5-Tap Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1100U-175/T&R | 制造商:Maxim Integrated Products 功能描述:IC DELAY LINE 5TAP 175NS 8UMAX |
| DS1100U-175/T&R | 功能描述:延遲線/計時元素 5-Tap Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1100U-175+ | 功能描述:延遲線/計時元素 5-Tap Timing Element RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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