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參數資料
| 型號： | DS1100LZ-75 |
| 英文描述： | 3.3V 5-Tap Economy Timing Element Delay Line |
| 中文描述： | 3.3 5抽頭經濟定時元素延遲線 |
| 文件頁數： | 5/6頁 |
| 文件大?。?/td> | 156K |
| 代理商： | DS1100LZ-75 |
DS1100L
5 of 6
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
25°C ±3°C
3.3V ±0.1V
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
50 max
3.0ns max (measured between 10% and 90%)
500ns (1
μ
s for -500 version)
1
μ
s (2
μ
s for -500 version)
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1100L-40 | 3.3V 5-Tap Economy Timing Element Delay Line |
| DS1100L-45 | 3.3V 5-Tap Economy Timing Element Delay Line |
| DS1100L-50 | 3.3V 5-Tap Economy Timing Element Delay Line |
| DS1100L-500 | 3.3V 5-Tap Economy Timing Element Delay Line |
| DS1100L-75 | 3.3V 5-Tap Economy Timing Element Delay Line |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS1100LZ-75/T&R | 制造商:Maxim Integrated Products 功能描述:DL 3V 8PIN 5TAP 75NS SOIC TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC DELAY LINE 5TAP 75NS 8SOIC |
| DS1100LZ-75/T&R+W | 制造商:Maxim Integrated Products 功能描述:ACTV TAPPED DLY LINE 5 TAP 1-IN 15NS ABS 75NS MAX 8SOIC N - Tape and Reel |
| DS1100LZ-75/T&R | 功能描述:延遲線/計時元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1100LZ-75/T&R+W | 功能描述:延遲線/計時元素 3V 5-Tap Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| DS1100LZ-75+ | 功能描述:延遲線/計時元素 3V 5-Tap Delay Line RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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