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參數(shù)資料
| 型號(hào)： | DS1100-300 |
| 英文描述： | 5-Tap Economy Timing Element Delay Line |
| 中文描述： | 5抽頭經(jīng)濟(jì)定時(shí)元素延遲線 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | DS1100-300 |
DS1100
5 of 6
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100.
The input waveform is produced by a precision-pulse generator under software control. Time delays are
measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap
is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT :
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
+25°C ±3°C
5.0V ±0.1V
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
50 max
3.0ns max (measured between 0.6V and 2.4V)
500ns (1μs for -500 version)
1μs (2μs for -500 version)
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1100-35 | 5-Tap Economy Timing Element Delay Line |
| DS1100-40 | 6 Pin, DIP, Zero Crossing Triac Detector, VDRM 400V, IFT 5mA Optocoupler |
| DS1100-45 | 5-Tap Economy Timing Element Delay Line |
| DS1100-50 | 6 Pin, DIP, Zero Crossing Triac Detector, VDRM 600V, IFT 5mA Optocoupler |
| DS1100-500 | 6 Pin, DIP, Zero Crossing Triac Detector, VDRM 600V, IFT 30mA Optocoupler |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1100-35 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:5-Tap Economy Timing Element Delay Line |
| DS1100-40 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:5-Tap Economy Timing Element Delay Line |
| DS1100-45 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:5-Tap Economy Timing Element Delay Line |
| DS1100-50 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:5-Tap Economy Timing Element Delay Line |
| DS1100-500 | 制造商:DALLAS 制造商全稱(chēng):Dallas Semiconductor 功能描述:5-Tap Economy Timing Element Delay Line |
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