參數(shù)資料
型號(hào): DS1085L
英文描述: 3.3V EconOscillator Frequency Synthesizer
中文描述: 3.3V EconOscillator頻率合成器
文件頁數(shù): 5/14頁
文件大小: 622K
代理商: DS1085L
D
DS1086 Spread-Spectrum EconOscillator
_____________________________________________________________________
5
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (continued)
(V
CC
= 5V ±5%, T
A
= 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITION
MIN
0.6
4.0
TYP
MAX
UNITS
Fast mode
Standard mode
Setup Time for STOP
t
SU:STO
μs
Capacitive Load for Each Bus
Line
C
B
(Note 16)
400
pF
NV Write-Cycle Time
Input Capacitance
t
WR
C
I
10
ms
pF
5
Note 1:
Note 2:
All voltages are referenced to ground.
DAC and OFFSET register settings must be configured to maintain the clock frequency within this range. Correct opera-
tion of the device is not guaranteed if these limits are exceeded.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
A
= +25°C.
This is the percentage frequency change from the +25°C frequency due to temperature at V
CC
= 5V. The maximum tem-
perature change varies with the master frequency setting. The minimum occurs at the default master frequency (f
default
).
The maximum occurs at the extremes of the output frequency range (66MHz or 133MHz) (see Figure 2).
The dither deviation of the master frequency is unidirectional and lower than the undithered frequency.
The integral nonlinearity of the frequency adjust DAC is a measure of the deviation from a straight line drawn between the
two endpoints of a range. The error is in percentage of the span.
This is true when the prescaler = 1.
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original
value to the new value.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
stab
is equivalent to approximately 512 master clock cycles and therefore
depends on the programmed clock frequency.
Output voltage swings can be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
> 250ns must then be met.
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
R MAX
+ t
SU:DAT
=
1000ns + 250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
IH MIN
of the SCL sig-
nal) in order to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
C
B
—total capacitance of one bus line, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
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