參數(shù)資料
型號: DS1077
英文描述: 10/100/1000 Base-T Ethernet LAN Switch
中文描述: EconOscillator™/分頻器
文件頁數(shù): 16/21頁
文件大?。?/td> 286K
代理商: DS1077
DS1077
16 of 21
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(-40 C to +85 C; V
CC
= 5V±5%)
TYP
MAX
PARAMETER
SYMBOL
CONDITION
MIN
UNITS
NOTES
Fast Mode
Standard Mode
Fast Mode
Standard Mode
400
100
SCL Clock Frequency
f
SCL
kHz
1.3
4.7
Bus Free Time
Between a STOP
and START Condition
Hold Time (Repeated)
START Condition
LOW Period of SCL
t
BUF
μs
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
Fast Mode
Standard Mode
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
100
250
t
HD
:
STA
μs
6
t
LOW
μs
HIGH Period of SCL
t
HIGH
μs
Set-Up Time for a
Repeated START
Data Hold Time
t
SU
:
STA
μs
t
HD
:
DAT
0.9
μs
7,8
Data Set-Up Time
t
SU
:
DAT
ns
300
1000
300
Rise Time of Both
SDA and SCL Signals
Fall Time of Both SDA
and SCL Signals
Set-Up Time For STOP
t
R
20 + 0.1
C
B
ns
9
t
F
20 + 0.1
C
B
ns
9
0.6
4.0
t
SU
:
STO
μs
Capacitive Load for
Each Bus Line
Input Capacitance
C
B
400
pF
9
C
I
5
pF
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER
SYMBOL
Writes
CONDITION
+85
°
C
MIN
10,000
TYP
MAX
UNITS
NOTES
NOTES:
1)
All voltages are referenced to ground.
2)
8.13kHz is obtained from a -66MHz standard part.
3)
PDN is a power-down signal applied to either CTRL0 or CTRL1 pins as appropriate.
4)
Output voltage swings may be impaired at high frequencies combined with high output loading.
5)
After this period, the first clock pulse is generated.
6)
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
M
IN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7)
The maximum t
HD
:
DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL
signal.
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