參數(shù)資料
型號(hào)： DS1075Z-100IND
英文描述： Oscillator/Divider
中文描述： 振蕩器/除法
文件頁(yè)數(shù)： 12/12頁(yè)
文件大?。?/td> 183K
代理商： DS1075Z-100IND
DS1073
12 of 12
AC ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C) (V
CC
=3.15V ± 10%)
CONDITION
MIN
TYP
PARAMETER
SYMBOL
MAX
UNIT
S
NOTE
S
Output Frequency
Accuracy
f
O
V
CC
= 3.15V,
T
A
=25 C
Over temp and
voltage
-0.5
0
+0.5
%
Combined Freq. Variation
f
O
-2.5%
2.5%
%
Long Term Stability
Minimum Output
Frequency
Power-Up Time
Enable OUT from
PDN
↑
Enable OUT0 from
PDN
↑
OUT Hi-Z from
PDN
↓
OUT0 Hi-Z from
PDN
↓
Load Capacitance
(IN/OUT, OUT0)
Output Duty Cycle
IN/OUT
OUT0
f
O
-0.5
+0.5
%
f
OUT
29.3
kHz
1
t
POR
+t
STAB
t
STAB
t
STAB
t
PDN
t
PDN
0.1
0.1
0.1
1
1
1
1
1
ms
ms
ms
ms
ms
2.3
3
3,4
C
L
15
pF
5
40
40
60
60
%
%
T Setup Enable Master
T
SUEM
MCLK=100
MHz
20
ns
Jitter
J
100
pS
6
NOTES:
1.
The values of M and N must be chosen so that this specification is met.
2.
This is the time from when V
CC
is applied until the output starts oscillating.
3.
When the device is initially powered up or restored from the power-down mode, OE should be
asserted (high). Otherwise the start of the t
STAB
interval will be delayed until OE goes high. OE can
subsequently be returned to a low level during the t
STAB
interval to force out low after the t
STAB
interval. If the external mode is selected, t
STAB
will be a function of the OSCIN period, i.e. external
clock frequency. See “Calculated Parameters” to determine the value of t
STAB
in this case.
4.
Although OE does not normally affect OUT0 operation, if OE is held low during power-up, the start
of the t
STAB
period will be delayed until OE is asserted. If OE remains low, OUT0 will not start.
5.
Operation with higher capacitive loads is possible but may impair output voltage swing and maximum
operation frequency.
6.
Parameter given is typical at 3 sigma.
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