參數(shù)資料
型號(hào): DS1073
英文描述: EconOscillator/Divider
中文描述: EconOscillator /分頻器
文件頁數(shù): 9/18頁
文件大?。?/td> 260K
代理商: DS1073
DS1073
9 of 18
POWER-UP
When
PDN
is taken to a high level the following power-up sequence occurs:
1.
Enable internal oscillator and/or OSCIN buffer.
2.
Set M and N to maximum values.
3.
Wait approximately 256 cycles of MCLK for it to stabilize.
4.
Reset M and N to programmed values.
5.
Enable OUT0 (assuming
EN0
bit = 0).
6.
Enable OUT.
Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs.
Figure 9
POWER-ON RESET
When power is initially applied to the device supply pin, a power-on reset sequence is executed, similar
to that which occurs when the device is restored from a power-down condition. This sequence comprises
two stages, first a conventional POR to initialize all on-chip circuitry, followed by a stabilization period
to allow the oscillator to reach a stable frequency before enabling the outputs:
1.
Initialize internal circuitry.
2.
Enable internal oscillator and/or OSCIN buffer.
3.
Set M and N to maximum values.
4.
Wait approximately 256 cycles of MCLK for the oscillator to stabilize.
5.
Load M and N programmed values from EEPROM.
6.
Enable OUT0 (assuming EN0 = 0).
7.
Enable OUT.
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