參數(shù)資料
型號: DS1040M-B40
廠商: DALLAS SEMICONDUCTOR
元件分類: Delay Line
英文描述: PULSE GENERATOR DELAY LINE, COMPLEMENTARY OUTPUT, PDIP8
封裝: 0.300 INCH, DIP-8
文件頁數(shù): 5/6頁
文件大?。?/td> 111K
代理商: DS1040M-B40
DS1040
5 of 6
POWER-UP TIMING DIAGRAM Figure 3
TEST CIRCUIT Figure 4
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first trigger pulse and the leading edge of the
following trigger pulse.
tWIH , WIL , WO (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge
and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the
leading edge.
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