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參數(shù)資料
| 型號(hào)： | DS1033Z-8+W |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 8NS 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 功能： | 多個(gè)，不可編程 |
| 延遲到第一抽頭： | 8ns |
| 可用的總延遲： | 8ns |
| 獨(dú)立延遲數(shù)： | 3 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
DS1033
5 of 6
TEST CONDITIONS
Ambient Temperature:
25
°C ±=3°C
Supply Voltage (VCC):
3.3V
±=0.1V
Input Pulse:
High: 3.0V
±=0.1V
Low: 0.0V
±=0.1V
Source Impedance: 50
=max.
Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1
s
Output Load Capacitance: 15 pF
Output:
Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
TIMING DIAGRAM
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive with respect to de-coupling, layout, etc.
3. VCC=3.3V
±=10%.
4. VCC=2.7V.
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