參數(shù)資料
型號: DS1020-100
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Delay Line
英文描述: SILICON DELAY LINE, TRUE OUTPUT, PDIP16
封裝: 0.300 INCH, LOW PROFILE, DIP-16
文件頁數(shù): 8/9頁
文件大?。?/td> 191K
代理商: DS1020-100
DS1020
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
相關(guān)PDF資料
PDF描述
DS1020-25 SILICON DELAY LINE, TRUE OUTPUT, PDIP16
DS1020S-200 SILICON DELAY LINE, TRUE OUTPUT, PDSO16
DS1020S-50 SILICON DELAY LINE, TRUE OUTPUT, PDSO16
DS1020-200 SILICON DELAY LINE, TRUE OUTPUT, PDIP16
DS1020S-100 SILICON DELAY LINE, TRUE OUTPUT, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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