參數(shù)資料
型號: DS-113
英文描述: Two-Way Power Divider 400 kHz400 MHz
中文描述: 雙向功分400 kHz400兆赫
文件頁數(shù): 2/7頁
文件大?。?/td> 226K
代理商: DS-113
DS1200
2 of 7
Figure 1. ELECTRONIC TAG BLOCK DIAGRAM
Figure 2. ADDRESS/COMMAND
OPERATION
The block diagram (Figure 1) illustrates the main elements of the device: shift register, control logic,
NV RAM, and power switch. To initiate a memory cycle, RST is taken high and 24 bits are loaded into
the shift register, providing both address and command information. Each bit is input serially on the
rising edge of the CLK input. Seven address bits specify one of the 128 RAM locations. The remaining
command bits specify read/write and byte/burst mode. After the first 24 clocks, which load the shift
register, additional clocks will output data for a read or input data for a write. The number of clock pulses
equal 24 plus 8 for byte mode or 24 plus 1024 for burst mode.
For hardwired applications, active power is supplied by the VCC pin. Alternatively, for user-insertable
applications, power can be supplied by the RST pin.
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