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參數(shù)資料
| 型號： | DPSD32MX8TY5-DP-XXP13 |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM, PDSO54 |
| 封裝： | STACKED, TSOP2-54 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 138K |
| 代理商： | DPSD32MX8TY5-DP-XXP13 |
PIN NAMES
A0-A11
Row Address:
A0-A11
Column Address:
A0-A9, A11
BA0, BA1
Bank Select Address
DQ0-DQ7
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
DQM
Data Input/Output Mask
CKE
Clock Enable
CLK
System Clock
CS
Chip Select
VCC/VSS
Power Supply/Ground
VCCQ/VSSQ
Data Output Power/Ground
NC
No Connect
30A213-00
REV. D 6/03
This document contains information on a product that is currently released to production at DPAC Technologies.
DPAC reserves the right to change products or specifications herein without prior notice.
256 Megabit Synchronous DRAM
DPSD32MX8TY5
1
ADVANCE D COM P ON E NTS PACKAG I N G
DESCRIPTION:
The Memory Stack series is a family of interchangeable memory devices. The 256 Megabit Syncronous DRAM assembly
utilizes the space saving LP-Stack technology to increase memory density. This stack is constructed with two 128Mb
(32M x 4) SDRAMs.
This 256Mb LP-Stack has been designed to fit in the
same footprint as the 128Mb (32M x 4) SDRAM TSOPII
monolithic. This stack allows for system upgrade while
providing an alternative low cost memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers’ datasheets
Memory organization:
(2) 128Mb memory devices. Each device arranged
as 32M x 4 bits (8M x 4 bits x 4 banks)
Memory stack organization:
32M x 8 bits (8M x 8 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and
footprint (with 1 CS, 1 CKE, DQ0-DQ7)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
PIN-OUT DIAGRAM
1
33 A8
VCC
1
2
54 VSS
VCCQ
3
53
NC
4
52 VSSQ
DQ1
5
51 NC
VSSQ
6
50 DQ6
NC
7
49 VCCQ
8
48 NC
VCCQ
9
47
NC 10
46 VSSQ
DQ3 11
45 NC
VSSQ 12
44 DQ4
NC 13
43 VCCQ
VCC 14
42 N.C.
N.C. 15
41 VSS
WE 16
40 NC
CAS 17
39 DQM
RAS 18
38 CLK
CS 19
37 CKE
BA0 20
36 A12
BA1 21
35 A11
A10 22
34 A9
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VCC 27
28 VSS
DQ2
DQ0
DQ5
DQ7
(TOP VIEW)
FUNCTIONAL BLOCK DIAGRAM
A0-A11
CAS
WE
128
Mb
SDRAM
DQ0-DQ7
CS
(8M
x
4bit
x
4bank)
RAS
CKE
CLK
DQM
BA0,BA1
(8M
x
4bit
x
4
bank)
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