參數(shù)資料
型號(hào)： DPSD32ME8TKY5-DP-XX75P2
元件分類： DRAM
英文描述： 32M X 8 SYNCHRONOUS DRAM MODULE, PDSO54
封裝： STACKED, TSOP2-54
文件頁(yè)數(shù)： 1/2頁(yè)
文件大小： 140K
代理商： DPSD32ME8TKY5-DP-XX75P2
PIN NAMES
A0-A11
Row Address:
A0-A11
Column Address:
A0-A9
BA0, BA1
Bank Select Address
DQ0-DQ7
Data In/Data Out
CAS
Column Address Strobe
RAS
Row Address Strobe
WE
Data Write Enable
DQM
Data Input/Output Mask
CKE0,CKE1
Clock Enables
CLK
System Clock
CS0, CS1
Chip Selects
VCC/VSS
Power Supply/Ground
VCCQ/VSSQ
Data Output Power/Ground
NC
No Connect
DESCRIPTION:
The Memory Stack series is a family of interchangeable memory devices. The 256 Megabit SDRAM assembly utilizes the
space saving LP-Stack technology to increase memory density. This stack is constructed with two 128Mb
(16M x 8) SDRAMs.
This 256Mb LP-Stack has been designed to fit in the
same footprint as the 128Mb (16M x 8) SDRAM TSOPII
monolithic. This stack allows for system upgrade without
electrical or mechanical redesign, providing an
alternative low cost memory solution.
FEATURES:
Electrical characteristics meet semiconductor
manufacturers’ datasheets
Memory organization:
(2) 128Mb memory devices. Each device arranged
as 16M x 8 bits (4M x 8 bits x 4 banks)
Memory stack organization:
32M x 8 bits (8M x 8 bits x 4 banks)
JEDEC approved, 2 Rank stack pinout and
footprint (with 2 CSs and 2 CKEs)
Optimized for RDIMMs
IPC-A-610, class 2, manufacturing standards
Lead free manufacturing process
Package: 54-Pin TSOPII stack
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
256 Megabit Synchronous SDRAM
DPSD32ME8TKY5
1
ADVANCE D COM P ON E NTS PACKAG I N G
30A226-01
REV. B 6/03
PIN-OUT DIAGRAM
(TOP VIEW)
33
A8
VCC
1
DQ0
2
54
VSS
VCCQ
3
53
DQ7
NC
4
52
VSSQ
DQ1
5
51
NC
VSSQ
6
50
DQ6
NC
7
49
VCCQ
DQ2
8
48
NC
VCCQ
9
47
DQ5
NC
10
46
VSSQ
DQ3
11
45
NC
VSSQ
12
44
DQ4
NC
13
43
VCCQ
VCC
14
42
NC
CS1
15
41
VSS
WE
16
40
CKE1
CAS
17
39
DQM
RAS
18
38
CLK
CS0
19
37
CKE0
BA0
20
36
NC
BA1
21
35
A11
A10
22
34
A9
A0
23
32
A7
A1
24
31
A6
A2
25
30
A5
A3
26
29
A4
VCC
27
28
VSS
1
FUNCTIONAL BLOCK DIAGRAM
CAS
WE
DQ0-DQ7
CS0
RAS
CS1
CLK
A0-A11
CKE1
CKE0
BA0,BA1
(4M
x
8
bits
x
4
banks)
128
Mb
SDRAM
(4M
x
8
bits
x
4
banks)
相關(guān)PDF資料
PDF描述
DPSD32ME8TKY5-DP-XX75 32M X 8 SYNCHRONOUS DRAM MODULE, PDSO54
DPU02DS PIANO DIP SWITCH-2SWITCHES, SPST, MOMENTARY,THROUGH HOLE-STRAIGHT
DPU05DS PIANO DIP SWITCH-5SWITCHES, SPST, MOMENTARY,THROUGH HOLE-STRAIGHT
DPX201990DT-4011D1 1850 MHz(Tx), 892 MHz(Rx), DUPLEXER
DPX202170DT-4021A1 2045 MHz(Tx), 857.5 MHz(Rx), DUPLEXER
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