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參數(shù)資料
| 型號： | DPS1MX32ML-35C |
| 元件分類： | SRAM |
| 英文描述： | 1M X 32 MULTI DEVICE SRAM MODULE, 35 ns, ZMA72 |
| 封裝： | LEADED, ZIP-72 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 587K |
| 代理商： | DPS1MX32ML-35C |
Dense-Pac Microsystems, Inc.
DPS1MX32ML/DPS1MX32MW
NOTES:
1. The PD0 - PD3 pins are used to identify memory density when other density versions of the JEDEC STD module can be installed
in the same socket.
2. All voltages are with respect to VSS.
3. -2.0V min. for pulse width less than 20ns (VIL min.= -0.5V at DC level).
4. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
5. This parameter is guaranteed and not 100% tested.
6. Transition is measured at the point of
± 500mV from steady state voltage.
7. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs
must not be applied.
8. The outputs are in a high impedance state when WE is LOW.
WAVEFORM KEY
Data Valid
Transition from
Data Undefined
HIGH to LOW
LOW to HIGH
or Don’t Care
WRITE CYCLE 2: CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
30A147-00
REV. E
5
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