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參數(shù)資料
| 型號： | DNCM01 |
| 廠商： | Lineage Power |
| 英文描述： | 10/100 Ethernet MAC ASIC Macrocell(10/100 以太網(wǎng) MAC（媒體訪問控制） ASIC宏單元) |
| 中文描述： | 10/100以太網(wǎng)MAC的ASIC單元（10/100以太網(wǎng)的MAC（媒體訪問控制）的ASIC宏單元） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 374K |
| 代理商： | DNCM01 |
Advance Data Sheet
February 1997
4
Features
I
Compliant with ISO 8802.3
1995, and
IEEE
access control:
— Data transmission and reception rates of
10 Mbits/s at a clock speed of 2.5 MHz or
100 Mbits/s at a clock speed of 25 MHz.
— State machines for implementing the MII inter-
face support standards-based connectivity to a
variety of physical layer devices (PHYs).
— Transmits or receives at full- or half-duplex.
— Supports flow control.
— Supports both Level 1 and Level 2 VLAN frame
recognition.
1993,
IEEE
*
802.3u
802.3x
1995 standards for media
I
Extensive network management signals are pro-
vided.
I
Transmit and receive functions can be asynchro-
nously reset with no clocks present.
I
Supports full internal scan test methodology.
I
Designed using
Verilog
HDL.
I
Suitable for Lucent Technologies’ 0.5
0.35
μ
m CMOS technology (3 V or 5 V operation).
A kit part and evaluation board is planned for eval-
uating the macrocell:
— The kit part provides a CPU interface for regis-
tered access to configuration and status signals,
management counters, and the MII manage-
ment interface.
— All configuration and status signals also go to
pins to facilitate prototyping ASIC logic around
the macrocell.
μ
m and
I
I
Companion macrocells planned:
— 10 Mbits/s and 100 Mbits/s transceivers.
— Autonegotiation.
— Content addressable memory (CAM).
*
IEEE
Electronics Engineers, Inc.
Verilog
is a registered trademark of Cadence Design Systems,
Inc.
is a registered trademark of The Institute of Electrical and
Description
The DNCM01 is an 802.3u
cell capable of both 10 Mbits/s and 100 Mbits/s data
operation. The MAC interfaces with a transceiver
through a media independent interface (MII). The
transmit and receive clocks are 2.5 MHz or 25 MHz,
depending on which speed the PHY is running. The
DNCM01 supports half-duplex and full-duplex opera-
tion. The DNCM01 is capable of transmitting and
receiving MAC control frames, including the PAUSE
opcode. The DNCM01 allows full-duplex flow control
using the PAUSE opcode. The DNCM01 supports
both Level 1 and Level 2 VLAN tagging. The
DNCM01 is able to increase the maximum legal byte
count when frames are transmitted or received with
Level 1 or Level 2 VLAN tags. All transmit and
receive functions can be asynchronously reset with
no clocks present. The DNCM01 can be used with
full internal scan test methodology to ease test devel-
opment time and increase fault coverage.
1993 compliant macro-
This data sheet also describes the kit part for evalua-
tion of the DNCM01 macrocell. The kit part has a
CPU interface providing access to registers that
control transmit configuration and report transmit
status and receive status. The kit part configuration
signals are the logic OR of the configuration pins and
configuration register bits. The kit part status signals
are available as both register bits and output pins.
Figure 1 shows the DNCM01 block diagram.
DNCM01
10/100 Ethernet MAC ASIC Macrocell
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
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