參數(shù)資料
型號: DM93L09
文件頁數(shù): 67/158頁
文件大?。?/td> 2668K
代理商: DM93L09
Switching Characteristics
at V
CC
= 5V and T
A
= 25C ( for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
Enable to
Output, (Figure 1)
Enable to
Output, (Figure 1)
Data to
Output, (Figure 4)
Data to
Output, (Figure 4)
Address to
Output, (Figure 2)
Address to
Output, (Figure 2)
Clear to
Output, (Figure 3)
R
L
= 400
, C
L
= 15 pF
Min
Units
Max
28
t
PLH
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
High to Low Level Output
ns
t
PHL
27
ns
t
PLH
35
ns
t
PHL
28
ns
t
PLH
35
ns
t
PHL
35
ns
t
PHL
31
ns
Function Tables
E
L
H
L
C
H
H
L
Mode
Addressable Latch
Memory
Active High Eight
Channel Demultiplexer
Clear
H
L
Inputs
Present Output States
Q2
Q3
L
L
L
L
L
L
L
L
L
L
L
L
Mode
C
L
L
L
L
L
L
H
H
H
H
H
H
H
E
H
L
L
L
L
L
H
L
L
L
L
L
L
D
X
L
H
L
H
H
X
L
H
L
H
L
H
A0
X
L
L
H
H
A1
X
L
L
L
L
H
X
L
L
L
L
H
H
A2
X
L
L
L
L
Q0
L
L
H
L
L
Q1
L
L
L
L
H
Q4
L
L
L
L
L
Q5
L
L
L
L
L
Q6
L
L
L
L
L
Q7
L
L
L
L
L
Clear
Demultiplex
H
X
L
L
H
H
H
X
L
L
L
L
L
L
L
L
L
H
Q
N1
L
H
Q
N1
Q
N1
Memory
Q
N1
Q
N1
L
H
Q
N1
Q
N1
Q
N1
Q
N1
Q
N1
Addressable
Latch
H
H
H
H
Q
N1
Q
N1
Q
N1
Q
N1
L
H
X = Don’t Care Condition
L = Low Voltage Level
H = High Voltage Level
Q
N1
= Previous Output State
3
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