參數(shù)資料
型號(hào)： DM9161A
廠商： Electronic Theatre Controls, Inc.
英文描述： 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
中文描述： 10/100 Mbps快速以太網(wǎng)物理層單芯片收發(fā)器
文件頁(yè)數(shù)： 31/45頁(yè)
文件大小： 1206K
代理商： DM9161A
31
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name
Default
17.15
100FDX
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M full duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 100M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit. If this
bit is 1, it means the operation 1 mode is a 10M half duplex mode. The
software can read bit [15:12] to see which mode is selected after
auto-negotiation. This bit is invalid when it is not in the auto-negotiation
mode
Reserved
Read as 0, ignore on write
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the address
(bit 4). A station management entity connected to multiple PHY entities
must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written to
these bits
Auto-negotiation Monitor Bits
These bits are for debug only.The auto-negotiation status will be written to
these bits.
B3
b2 b1 B0
0
0
0
0
In IDLE state
0
0
0
1
Ability match
0
0
1
0
Acknowledge match
0
0
1
1
Acknowledge match fail
0
1
0
0
Consistency match
0
1
0
1
Consistency match fail
0
1
1
0
Parallel detects signal_link_ready
0
1
1
1
Parallel detects signal_link_ready fail
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-17.
9
17.8-17.4 PHYADR[4
Reserved
0, RO
:0]
(PHYADR),
RW
17.3-17.0 ANMB[3:0]
0, RO
17.3-17.0 ANMB[4:0]
0, RO
8.10 10BASE-T Configuration/Status (10BTCSR) - 18
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9161A_09 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
DM9161AEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161B 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DM9161BEP 制造商:DAVICOM 功能描述:IC TRX 10/100MBPS ENET PHY48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP 制造商:DAVICOM 功能描述:IC, TRX, 10/100MBPS, ENET PHY,48LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3 / 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:48; Interface Type:MII; Operating Temperature ;RoHS Compliant: Yes
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